Memory Layout Design Engineer

Role overview

Memory Layout Design Engineer at Broadcom

Understand and apply layout guidelines, new process rules, and technical requirements for high-quality layouts.

Job

Responsibilities

• Manage scheduling, timelines, and layout floor-planning.
• Ensure end-to-end deliverables are completed with high quality and within the planned schedule.
• Adapt quickly to new methodologies and communicate effectively with the SOC and library teams.
• Skill Set(Memory):
• Strong experience in memory layout design and physical verification (LVS, DRC, ERC, Antenna, Electro Migration).
• Experience with Cadence Layout tools (Virtuoso XL, VXL, or EXL) and Calibre verification tools.
• Proficiency in floor-planning, hierarchy layout, and chip integration.
• Solid understanding of memory architecture and RC requirements, with the ability to plan signal and power routing.
• Ability to lead teams, train junior engineers, and manage projects effectively.
• Ability to lead new technology reviews to document layout methodologies, flows, and guidelines.
• Self-reliant with the ability to work both independently and collaboratively.
• Broadcom is proud to be an equal opportunity employer.
• We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law.
• We will also consider qualified applicants with arrest and conviction records consistent with local law.
• If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

Required qualifications

• Bachelor's degree with 12 years of experience or a Master's degree with over 10 years of experience.
• Proficiency in using Cadence tools (Virtuoso Layout, Layout XL, Cadence Schematic Capture, and verification tools - Calibre & Hercules).
• Strong layout knowledge in submicron processes (e.g., 7nm, 5nm, 3nm, 2nm).

Preferred qualifications and skills

• Strong knowledge of memory layout topology; experience with memory compilers is preferred.
• Knowledge of AI, layout automation, and script/SKILL programming is preferred.

Employment details

• Location: IND-Bangalore Electronic City - S1 [India]

Application details

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