ASIC Engineering Digital Design Leader (Digital design, FSM, CPU sub-systems, complex SOCs | 12-16 Years | Pune/ Bangalore)

Role overview

ASIC Engineering Digital Design Leader (Digital design, FSM, CPU sub-systems, complex SOCs | 12-16 Years | Pune/ Bangalore) at Cisco

Responsibilities

• Lead the full ASIC lifecycle, from RTL design to post-silicon support, and collaborate with cross-functional teams.

Employment details

• Location: Pune [India], Bangalore [India]

Additional role details

• Become part of our team as the ASIC Engineering Digital Design Leader, providing technical leadership in the development of digital logic for silicon photonics.
• Ideal for experienced professionals in high-speed optical interconnects and ASIC/SoC design.