ASIC Engineering Design Verification Leader (SystemVerilog, Python, C and UVM |8-12 years| Pune)

Role overview

ASIC Engineering Design Verification Leader (SystemVerilog, Python, C and UVM |8-12 years| Pune) at Cisco

Employment details

• Location: Pune [India]

About the employer

• We are recruiting a ASIC Engineering Design Verification Leader to drive the design and verification of advanced optical transceivers and platforms for Cisco's data centre networking solutions.

Additional role details

• Lead verification documentation, develop testbench components, and collaborate with multidisciplinary teams.
• Ideal for experienced engineers with strong expertise in SystemVerilog, Python, C, and UVM.