Design Verification Engineer, Silicon Engineering
Google · Bangalore
Collected role description
Role overview
Design Verification Engineer, Silicon Engineering at Google
Required qualifications
- Minimum qualification: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.; 4 years of experience verifying digital logic at RTL using System Verilog for FPGAs and ASICs.; Experience with UVM Testbenches/environments.
Preferred qualifications and skills
- Preferred qualification: Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.; Expertise in creating/using verification components and environments in UVM methodology at IP or Subsystem level.; Experience with image processing, computer vision or machine learning IPs.; Experience with AMBA(APB/AXI/ACE) or other standard protocols.; Familiarity with CPU, GPU or other compute/ML architectures.; Excellent communication and collaboration skills with the ability to work with cross-functional teams.
Employment details
- Location: Bengaluru [Karnataka] [India]
Application details
- Information collected and processed as part of your Google Careers profile, and any job applications you choose to submit is subject to Google's Applicant and Candidate Privacy Policy .
About the employer
- Google is proud to be an equal opportunity and affirmative action employer.
- Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting.
- Please do not forward resumes to our jobs alias, Google employees, or any other organization location.
Additional role details
- We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents-to-be, criminal histories consistent with legal requirements, or any other basis protected by law.
- See also Google's EEO Policy , Know your rights: workplace discrimination is illegal , Belonging at Google , and How we hire .
- If you have a need that requires accommodation, please let us know by completing our Accommodations for Applicants form .
- To all recruitment agencies: Google does not accept agency resumes.
- Google is not responsible for any fees related to unsolicited resumes.
- Equity is granted exclusively and discretionarily by Alphabet Inc. on the basis of an agreement concluded between you and Alphabet Inc.
- Alphabet Inc. is your sole contractual partner with respect to equity grants.
- GSU grants are not guaranteed, are discretionary, are subject to approval by the Alphabet Inc. board of directors or its delegate, the terms of the relevant Alphabet Inc. stock plan, and your grant agreement.
- They have no impact on statutory payments.
- Current or past grants do not confer an acquired right.
Collected minimum qualification
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.; 4 years of experience verifying digital logic at RTL using System Verilog for FPGAs and ASICs.; Experience with UVM Testbenches/environments.
Collected preferred qualification
Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.; Expertise in creating/using verification components and environments in UVM methodology at IP or Subsystem level.; Experience with image processing, computer vision or machine learning IPs.; Experience with AMBA(APB/AXI/ACE) or other standard protocols.; Familiarity with CPU, GPU or other compute/ML architectures.; Excellent communication and collaboration skills with the ability to work with cross-functional teams.
Collected experience requirement
4 years of experience verifying digital logic at RTL using System Verilog for FPGAs and ASICs.