Senior Designer

Role overview

Senior Designer at HCLTech

Role Summary Execute core platform software sustenance tasks — bootloader, power management and core kernel work — reporting to the Pod Lead.

Pod 2 — Coretech — Senior Engineer Pod / Track Pod 2 — Coretech Role Title Senior Engineer — Core Platform Software (Bootloader, Power Management & Kernel Core) Experience 5 – 8 years Primary Location Hyderabad, India (Transition phase); HCLTech Offshore Delivery Center thereafter Work Model Physical co-location at Hyderabad mandatory during Transition (Month 1–3) for knowledge transfer and hardware/lab access; delivery shifts to HCLTech's Offshore Delivery Center (ODC) from Shadow (Month 4–6) onward.

Responsibilities

• Implement and validate fixes for bootloader, power management, clock/regulator and core kernel defects.
• Implement fixes for peripheral driver, memory driver, and DSP/NPU firmware defects within the SoC infrastructure layer.
• Debug SoC bring-up issues, power sequencing failures, and core driver regressions.
• Execute BSP core-layer validation against new chipset/firmware releases.
• Support customer escalations requiring core platform expertise.
• Must-Have Skills
• 5–8 years SoC bring-up or core platform software engineering.
• C, ARM architecture fundamentals.
• Linux kernel core subsystems.
• Power management frameworks (RPM/RPMh, clock/regulator).
• Bootloader development.
• JTAG / hardware debugger tooling.
• Non-HLOS/RTOS firmware and SoC infrastructure experience — peripheral drivers, memory drivers, DSP/NPU firmware.
• Good-to-Have Skills
• Hypervisor/virtualization exposure (Xen, Gunyah or equivalent).
• Upstream Linux kernel contribution history.
• Functional-safety or industrial temperature-range product experience.
• Bring-up experience across more than one SoC family/generation.
• Exposure to multiple firmware toolchains across DSP/NPU subsystems beyond the main applications processor.
• Skill Requirements Other Requirements

Employment details

• Location: Hyderabad [India]