DV Engineer at LTTS
LTTS · Bangalore
Collected role description
Role overview
DV Engineer at LTTS at LTTS
Key aspects include System Verilog, UVM (Universal Verification Methodology), and test planning Job Requirement DV Engineer
Responsibilities
- Design Verification (DV) Engineer tests and validates integrated circuit and semiconductor designs to ensure they are bug-free and meet functional specifications before manufacturing.
Employment details
- Location: Bangalore [India]
Additional role details
- Key aspects include System Verilog, UVM (Universal Verification Methodology), and test planning