Physical Design (PD) Engineer - Mixed-Signal SoC

Role overview

Physical Design (PD) Engineer - Mixed-Signal SoC at UAW Technologies India Private Limited (UANDWE)

Responsibilities

• Implementation Flow Ownership Drive full physical design flow: Synthesis, Floorplanning, Place and route (PnR), Clock tree synthesis (CTS), Physical verification and signoff Optimize for timing, power, and area (PPA) 5–12 years of physical design experience having worked on TSMC 22nm and below nodes Strong expertise in Synthesis and PnR tools (e.g., Cadence/Synopsys flows), STA and timing closure Experience with Advanced nodes and SoC integration, Multi-clock, multi-power domain designs

Required qualifications

• 5–12 years Skyworks is looking for a Physical Design Engineer to implement high-quality, low-power analog and digital blocks and subsystems within mixed-signal SoCs.
• You will be responsible for taking RTL through synthesis, place & route, and signoff, ensuring timing, power, and area targets are met.
• Past experience on TSMC, 22nm and below nodes.
• This role requires strong collaboration with RTL, DV, and analog teams to deliver silicon-ready designs.
• Minimum qualification: Bachelor's or Master's degree in Electronics/Electrical Engineering or related field

Preferred qualifications and skills

• Experience with mixed-signal SoC floorplanning Familiarity with IR drop, EM, signal integrity analysis Exposure to ARM Cortex-M or RISC-V based SoCs

Employment details

• Location: Bangalore [India]