DFT Principal Engineer
onsemi India · Bangalore
Collected role description
Role overview
DFT Principal Engineer at onsemi India
This group is responsible for development of Power management products including DC-DC PMIC/POL, Multiphase controllers, Dr. MOS, AC-DC converters, LED drivers, SiC drivers, Switches and efuses for consumer, industrial and automotive applications. #LI-VS1 In this role, you will focus on the following: DFT Lead with expertise various Scan implementation like Stuck-At, MBIST, iJTAG, BSCAN, Transition, bridge faults Providing timing constraints for scan modes Pattern simulation with zero delay and SDF Coverage analysis and improvement suggestions to design Low power issues fix post DFT implementation Post silicon debug Solid understanding of Verilog, TCL and Perl/Python/XML programming languages Strong in problem solving with deep understanding of technical issues.
Required qualifications
- Candidate should have keen eye to improve existing flow and methods with positive impact on PPA. #LI-VS1 Qualifications BS in Electrical Engineering or related + 12 years of experience, or MS + 11 years of experience in working and leading Digital Design, Architecture and ASIC/Mixed signal chip developments Solid understanding of RTL design, CDC, ASIC synthesis, timing analysis and CDC, P&R, UPF Solid understanding of Verilog, TCL and Perl/Python/XML programming languages Solid track record of releasing complex ICs to market Ability to clearly articulate issues, challenges, and concerns to all levels of management Must have good written and verbal cross-functional communication skills #LI-VS1
Employment details
- Location: Bangalore [Karnataka] [India]
Additional role details
- OnSemi is seeking a Principal Physical DFT Engineer, NEW PRODUCT DEVELOPMENT, Power Management, to join our growing team in Bengaluru, India.
Collected minimum qualification
Solid understanding of RTL design, CDC, ASIC synthesis, timing analysis and CDC, P&R, UPF
Collected experience requirement
BS in Electrical Engineering or related + 12 years of experience, or MS + 11 years of experience in working and leading Digital Design, Architecture and ASIC/Mixed signal chip developments