LEAD PLATFORM EMULATION ENGINEER

AMD · Bangalore

Collected role description

ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career. LEAD PLATFORM EMULATION ENGINEER: THE ROLE: The focus of this role is to plan, build, execute the verification, validation/emulation and debug of new and existing features for AMD’s SOCs, resulting in no bugs in the final SOC design and the firmware/BIOS. This senior role will stretch you as you lead emulation team in new directions, network with our world-class, patent-holding think-tank, and negotiate amongst design teams, marketing, and business unit executives. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification/debugging in general. You are a team player who has experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problemsYou have excellent communication and presentation skills, demonstrated through technical publications, presentations, trainings, executive briefings, etc. You are highly adept at collaboration among top-thinkers and engineers alike, ready to mentor and guide, and help to elevate the knowledge and skills of the team around you. KEY RESPONSIBILITIES: <ul><li>Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified</li><li>Drive Emulation Methodologies, SOC Design Model and Test Architecture for full chip SOC and hybrid models </li><li>Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases</li><li>Estimate the time required to write the new feature tests and any required changes to the test environment </li><li>Build the directed Pre-Silicon Emulation tests</li><li>Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test or infra issues</li><li>Responsible for writing directed tests to verify features in a co-simulated and emulated/FPGA hardware environment</li><li>Responsible for writing monitors and checkers to support end-to-end firmware/hardware validation</li><li>Responsible for running emulator workloads to test new features and debug technical issues using logs, waveform dumps and RTL debug</li><li>Use AI for hardware debug, improve execution and emulation capacity efficiency and automation</li></ul> PREFERRED EXPERIENCE: <ul><li>Must have exposure to SOC architecture (preferred X86)</li><li>Experience with BIOS/OS bring up on full X86 SOC emulation platform</li></ul><ul><li>Proficient in IP level ASIC verification, experience working with CPU, GPU, and Memory subsystem</li><li>Proficient in debugging firmware and RTL code using simulation tools </li><li>Good understanding of PCIe/USB/Ethernet standards; safety concepts/IPs</li><li>Must have hands-on experience on Zebu/Palladium/Veloce platform to bring-up SOC</li><li>SOC design model build experience</li><li>Experienced with Verilog, System Verilog, C, and C++ </li><li>Experience in writing and debugging testbenches</li><li>Scripting language experience: Perl, Ruby, Makefile, shell preferred</li><li>Experience on debugging SOC IO interfaces with Transactor solutions in Emulation platform</li><li>Think differently and out of the box to stress the DUT in Emulation platform and verify it in efficient way</li><li>Should be open to learning verification methodologies and working closely with design, verification, validation, architecture and firmware teams</li><li>Excellent communication, management, and presentation skills</li><li>Adept at collaboration among top-thinkers and senior architects with strong interpersonal skills to work across teams in different geographies </li></ul> ACADEMIC CREDENTIALS:<ul><li>Bachelor’s or Master’s degree in Computer/Electronics/Electrical Engineering with 18+ years of experience</li></ul> Benefits offered are described: <a href="https://www.amd.com/en/corporate/careers/benefits.html" target="_blank" rel="noopener">AMD benefits at a glance</a>. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available <a href="https://www.amd.com/en/legal/responsible-ai-use-policy.html" target="_blank" rel="noopener">here.</a> This posting is for an existing vacancy.

Collected minimum qualification

Benefits offered are described:  <a href="https://www.amd.com/en/corporate/careers/benefits.html" target="_blank" rel="noopener">AMD benefits at a glance</a>. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD’s “Responsible AI Policy” is available <a href="https://www.amd.com/en/legal/responsible-ai-use-policy.html" target="_blank" rel="noopener">here.</a> This posting is for an existing vacancy.

Collected preferred qualification

LEAD PLATFORM EMULATION ENGINEER:  THE ROLE: The focus of this role is to plan, build, execute the verification, validation/emulation and debug of new and existing features for AMD’s SOCs, resulting in no bugs in the final SOC design and the firmware/BIOS. This senior role will stretch you as you lead emulation team in new directions, network with our world-class, patent-holding think-tank, and negotiate amongst design teams, marketing, and business unit executives. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification/debugging in general. You are a team player who has experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problemsYou have excellent communication and presentation skills, demonstrated through technical publications, presentations, trainings, executive briefings, etc. You are highly adept at collaboration among top-thinkers and engineers alike, ready to mentor and guide, and help to elevate the knowledge and skills of the team around you.  KEY RESPONSIBILITIES: <ul><li>Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified</li><li>Drive Emulation Methodologies, SOC Design Model and Test Architecture for full chip SOC and hybrid models </li><li>Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases</li><li>Estimate the time required to write the new feature tests and any required changes to the test environment </li><li>Build the directed Pre-Silicon Emulation tests</li><li>Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test or infra issues</li><li>Responsible for writing directed tests to verify features in a co-simulated and emulated/FPGA hardware environment</li><li>Responsible for writing monitors and checkers to support end-to-end firmware/hardware validation</li><li>Responsible for running emulator workloads to test new features and debug technical issues using logs, waveform dumps and RTL debug</li><li>Use AI for hardware debug, improve execution and emulation capacity  efficiency and automation</li></ul> PREFERRED EXPERIENCE: <ul><li>Must have exposure to SOC architecture (preferred X86)</li><li>Experience with BIOS/OS bring up on full X86 SOC emulation platform</li></ul><ul><li>Proficient in IP level ASIC verification, experience working with CPU, GPU, and Memory subsystem</li><li>Proficient in debugging firmware and RTL code using simulation tools </li><li>Good understanding of PCIe/USB/Ethernet standards; safety concepts/IPs</li><li>Must have hands-on experience on Zebu/Palladium/Veloce platform to bring-up SOC</li><li>SOC design model build experience</li><li>Experienced with Verilog, System Verilog, C, and C++   </li><li>Experience in writing and debugging testbenches</li><li>Scripting language experience: Perl, Ruby, Makefile, shell preferred</li><li>Experience on debugging SOC IO interfaces with Transactor solutions in Emulation platform</li><li>Think differently and out of the box to stress the DUT in Emulation platform and verify it in efficient way</li><li>Should be open to learning verification methodologies and working closely with design, verification, validation, architecture and firmware teams</li><li>Excellent communication, management, and presentation skills</li><li>Adept at collaboration among top-thinkers and senior architects with strong interpersonal skills to work across teams in different geographies </li></ul> ACADEMIC CREDENTIALS:<ul><li>Bachelor’s or Master’s degree in Computer/Electronics/Electrical Engineering with 18+ years of experience</li></ul>

Collected experience requirement

18+ years