PD Lead

<strong class="jdheading"></strong><br><br><p style="margin: 0px;"><span style="font-size: 12pt; font-family: arial, helvetica, sans-serif;"><strong>ADVANCE YOUR CAREER. ADVANCE THE WORLD. </strong></span></p><p style="margin: 0px;"><span style="font-size: 12pt; font-family: arial, helvetica, sans-serif;">At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. </span></p><p style="margin: 0px;"> </p><p style="margin: 0px;"><span style="font-size: 12pt; font-family: arial, helvetica, sans-serif;">Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career.</span></p> <br><strong class="jdheading"></strong><br><br><p style="margin: 0px;"><strong><span style="font-size: 12.0pt; font-family: 'Arial',sans-serif;">PMTS SILICON DESIGN ENGINEER<br><br></span></strong></p><p style="margin: 0px;"><strong>🔹</strong><strong> THE ROLE</strong></p><p style="margin: 0px;">As a <strong>PHY‑V Lead</strong>, you will own <strong>physical verification sign-off, full-chip integration, and packaging interface (RDL) planning</strong> for advanced SoC programs. You will drive <strong>DRC/LVS clean tapeouts, integration quality, and sign-off predictability</strong> across complex multi-IP designs.</p><p style="margin: 0px;">This role requires strong expertise in <strong>physical verification, top-level integration, and advanced packaging alignment</strong>, along with the ability to lead cross-functional execution across PD, Analog, and Packaging teams.</p><div align="center"><hr align="center" size="1" width="100%"></div><p style="margin: 0px;"><strong>🔹</strong><strong> THE PERSON</strong></p><ul type="disc"><li>Strong technical leader with <strong>deep PD + Physical Verification understanding</strong></li><li>Proven ownership of <strong>sign-off closure for complex SoCs</strong></li><li>Ability to drive execution across <strong>multiple teams and dependencies</strong></li><li>Detail-oriented with focus on <strong>quality, manufacturability, and schedule predictability</strong></li><li>Comfortable operating in <strong>high-pressure tapeout environments</strong></li></ul><div align="center"><hr align="center" size="1" width="100%"></div><p style="margin: 0px;"><strong>🔹</strong><strong> KEY RESPONSIBILITIES</strong></p><p style="margin: 0px;"><strong>✅</strong><strong> Physical Verification & Sign-off Ownership</strong></p><ul type="disc"><li>Drive end-to-end <strong>DRC, LVS, ERC, antenna closure</strong> at block and full-chip level</li><li>Define and enforce <strong>sign-off methodology and quality criteria</strong></li><li>Own foundry rule decks, waivers, and risk assessments</li><li>Deliver <strong>sign-off clean GDS for tapeout</strong></li></ul><div align="center"><hr align="center" size="1" width="100%"></div><p style="margin: 0px;"><strong>✅</strong><strong> SoC / Full-Chip Integration</strong></p><ul type="disc"><li>Lead <strong>top-level integration of IPs/macros into SoC</strong></li><li>Own:</li><ul type="circle"><li>GDS assembly</li><li>Hierarchical LVS reconciliation</li></ul><li>Resolve:</li><ul type="circle"><li>Boundary issues</li><li>Connectivity mismatches</li><li>Integration conflicts</li></ul><li>Ensure <strong>robust integration across internal and third-party IPs</strong></li></ul><div align="center"><hr align="center" size="1" width="100%"></div><p style="margin: 0px;"><strong>✅</strong><strong> RDL & Packaging Integration</strong></p><ul type="disc"><li>Drive <strong>RDL planning and bump mapping strategy</strong></li><li>Define IO escape routing and die–package interface</li><li>Collaborate with <strong>Packaging, SI/PI, and system teams</strong></li><li>Enable <strong>flip-chip / 2.5D / 3D integration readiness</strong></li></ul><div align="center"><hr align="center" size="1" width="100%"></div><p style="margin: 0px;"><strong>✅</strong><strong> Tapeout Execution & Tracking</strong></p><ul type="disc"><li>Own <strong>sign-off checklist, closure tracking, and tapeout readiness</strong></li><li>Lead <strong>tapeout reviews and milestone tracking</strong></li><li>Drive cross-team closure to meet <strong>schedule and quality targets</strong></li></ul><div align="center"><hr align="center" size="1" width="100%"></div><p style="margin: 0px;"><strong>✅</strong><strong> Methodology & Flow Development</strong></p><ul type="disc"><li>Define and improve <strong>physical verification flows (Calibre/ICV/Pegasus)</strong></li><li>Drive:</li><ul type="circle"><li>Automation (TCL/Python)</li><li>Runtime optimization</li><li>Debug efficiency</li></ul><li>Establish best practices for <strong>hierarchical and incremental sign-off</strong></li></ul><div align="center"><hr align="center" size="1" width="100%"></div><p style="margin: 0px;"><strong>✅</strong><strong> Debug & Issue Resolution</strong></p><ul type="disc"><li>Lead debug of:</li><ul type="circle"><li>Complex DRC violations</li><li>LVS mismatches (shorts/opens/connectivity issues)</li></ul><li>Drive closure with PD/layout teams</li><li>Minimize waivers and ensure <strong>risk-managed sign-off</strong></li></ul><div align="center"><hr align="center" size="1" width="100%"></div><p style="margin: 0px;"><strong>✅</strong><strong> Leadership & Collaboration</strong></p><ul type="disc"><li>Lead and mentor PHY‑V engineers</li><li>Act as <strong>primary escalation point for sign-off issues</strong></li><li>Interface with:</li><ul type="circle"><li>PD / PnR teams</li><li>Analog/layout teams</li><li>Packaging and foundry teams</li></ul></ul><div align="center"><hr align="center" size="1" width="100%"></div><p style="margin: 0px;"><strong>🔹</strong><strong> REQUIRED QUALIFICATIONS</strong></p><ul type="disc"><li>B.Tech / M.Tech in Electronics / Electrical Engineering</li><li><strong>10–15+ years</strong> in Physical Design / Physical Verification / SoC Integration</li><li>Strong expertise in:</li><ul type="circle"><li>DRC, LVS, ERC, antenna checks</li><li>Tools: <strong>Calibre / ICV / Pegasus</strong></li></ul><li>Solid understanding of:</li><ul type="circle"><li>Full PD flow (RTL → GDS → sign-off)</li><li>Advanced process nodes (7nm and below)</li></ul></ul><div align="center"><hr align="center" size="1" width="100%"></div><p style="margin: 0px;"><strong>🔹</strong><strong> PREFERRED QUALIFICATIONS</strong></p><ul type="disc"><li>Experience in:</li><ul type="circle"><li>Full-chip SoC integration and GDS assembly</li><li>RDL planning and advanced packaging flows</li></ul><li>Exposure to:</li><ul type="circle"><li>IR/EM, SI/PI, PEX, reliability checks</li><li>Chiplet / 2.5D / 3D-IC methodologies</li></ul><li>Strong scripting (TCL/Python) for automation</li><li>#LI-BM2</li></ul> <br><strong class="jdheading"></strong><br><br><p style="margin: 0px;"><span style="font-size: 12pt;"><em><span style="font-family: 'Arial',sans-serif; color: black;">Benefits offered are described: </span></em><span style="font-family: 'Arial',sans-serif; color: black;"><a href="https://www.amd.com/en/corporate/careers/benefits.html" target="_blank" rel="noopener">AMD benefits at a glance</a>.</span></span></p><p style="margin: 0px;"><span style="color: black; font-size: 12pt;"> </span></p><p style="margin: 0px;"><span style="font-size: 12pt;"><em><span style="font-family: 'Arial',sans-serif; color: black;">AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.</span></em></span></p><p style="margin: 0px;"><span style="color: black; font-size: 12pt;"> </span></p><p style="margin: 0px;"><span style="font-size: 12pt;"><em><span style="font-family: 'Arial',sans-serif; color: black;">AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available <a href="https://www.amd.com/en/legal/responsible-ai-use-policy.html" target="_blank" rel="noopener">here.</a></span></em></span></p><p style="margin: 0px;"><span style="font-size: 12pt;"><em><span style="font-family: 'Arial',sans-serif; color: black;"> </span></em></span></p><p style="margin: 0px;"><span style="font-size: 12pt;"><em><span style="font-family: 'Arial',sans-serif; color: black;">This posting is for an existing vacancy.</span></em></span></p>