LEC/CLP Engineer

AMD · Hyderabad

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Collected role description

Role overview

LEC/CLP Engineer at AMD

Responsible for LEC and CLP of all physical partitions of a device including its waivers, reviews and signoff

THE ROLE:

Responsibilities

Collaborate and support with design and/or implementation teams to achieve closure.
Drive this activity with set of engineers by planning work and presenting regular status.
Debug failure/issues and drive them to closure by working with CAD team or EDA vendor if required

Required qualifications

Minimum qualification: Benefits offered are described: AMD benefits at a glance . AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.

Preferred qualifications and skills

Highly Experienced in LEC and CLP with Synopsys or Cadence tool set.
Complete Understanding of synthesis and Low power flows including UPF
Have handled blocks with complex designs and their LEC/CLP lssues
Have debug experience to solve issues.
scripting and automation
ACADEMIC CREDENTIALS:
Bachelors with 6 years of experience or Masters degree with 4 year of experience in Electrical Engineering
#LI-AB1
Benefits offered are described: AMD benefits at a glance .
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services.
AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.
We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.
AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.

Employment details

Location: Hyderabad [India]

About the employer

At AMD, we believe technology has the power to solve the world’s most important challenges.

Benefits

From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future.

Additional role details

ADVANCE YOUR CAREER.
ADVANCE THE WORLD.
Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward.
Join us and, together, we’ll advance your career.
MTS LEC and CLP SILICON DESIGN ENGINEER
The focus of this role is to plan and execute the LEC and CLP of IP Subsystems and its signoff.
This involves ownership of LEC and CLP at all physical partition level.

Collected minimum qualification

Benefits offered are described:  <a href="https://www.amd.com/en/corporate/careers/benefits.html" target="_blank" rel="noopener">AMD benefits at a glance</a>. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD’s “Responsible AI Policy” is available <a href="https://www.amd.com/en/legal/responsible-ai-use-policy.html" target="_blank" rel="noopener">here.</a> This posting is for an existing vacancy.

Collected preferred qualification

<span style="margin: 0px; padding: 0px;" data-ccp-charstyle="normaltextrun" data-ccp-charstyle-defn="{"ObjectId":"75ee5cbf-7016-4753-9550-8bbf976473cd|105","ClassId":1073872969,"Properties":[469775450,"normaltextrun",201340122,"1",134233614,"true",469778129,"normaltextrun",335572020,"1",469778324,"Default Paragraph Font"]}">MTS LEC and CLP SILICON DESIGN ENGINEER<span style="margin: 0px; padding: 0px;" data-ccp-charstyle="eop" data-ccp-charstyle-defn="{"ObjectId":"75ee5cbf-7016-4753-9550-8bbf976473cd|106","ClassId":1073872969,"Properties":[469775450,"eop",201340122,"1",134233614,"true",469778129,"eop",335572020,"1",469778324,"Default Paragraph Font"]}">    THE ROLE: The focus of this role is to plan and execute the LEC and CLP of IP Subsystems and its signoff. This involves ownership of LEC and CLP at all physical partition level. KEY RESPONSIBILITIES:<ul><li>Responsible for LEC and CLP of all physical partitions of a device including its waivers, reviews and signoff</li><li>Collaborate and support with design and/or implementation teams to achieve closure.</li><li>Drive this activity with set of engineers by planning work and presenting regular status.</li><li>Debug failure/issues and drive them to closure by working with CAD team or EDA vendor if required</li></ul>  PREFERRED EXPERIENCE: <ul><li>Highly Experienced in LEC and CLP with Synopsys or Cadence tool set.</li><li>Complete Understanding of synthesis and Low power flows including UPF</li><li>Have handled blocks with complex designs and their LEC/CLP lssues</li><li>Have debug experience to solve issues.</li><li>scripting and automation</li></ul>  ACADEMIC CREDENTIALS:<ul><li>Bachelors with 6 years of experience or Masters degree with 4 year of experience in Electrical Engineering</li></ul>#LI-AB1

Collected experience requirement

6 years