Lead DFT DV Engineer

AMD · Hyderabad

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Collected role description

Role overview

Lead DFT DV Engineer at AMD

We are looking for an adaptive, self-motivative DFT engineer to join our growing team.

Responsibilities

LEAD DFT DV ENGINEER

Required qualifications

Minimum qualification: Benefits offered are described: AMD benefits at a glance . AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.

Preferred qualifications and skills

Good understanding and experience in DFT clocking and topology covering MBIST, JTAG verification, scan dump, understanding on ICL/PDL, debug scenarios like clock observation and analog observation, BScan, HSIO tests experience
Experience in multi die scenarios verification is preferable
Work closely with design /Arch team to prepare test list and complete the verification with all planned tests
Develop scalable verification platform in System Verilog / UVM.
Able to guide team in writing assertions and checkers.
Be responsible for a comprehensive verification plan and drive the implementation of verification tests
Responsible for SCAN, MBIST and JTAG verification
ACADEMIC CREDENTIALS:
Bachelors degree w/7+ years or Masters degree w/5+ years in Electronics engineering/Electrical Engineering
#LI-AB1
Benefits offered are described: AMD benefits at a glance .
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services.
AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.
We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.
AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.

Employment details

Location: Hyderabad [India]

About the employer

At AMD, we believe technology has the power to solve the world’s most important challenges.
As a key contributor, you will be part of a leading team to drive and improve AMD's abilities to deliver the highest quality, industry-leading technologies to market.

Benefits

From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future.

Additional role details

ADVANCE YOUR CAREER.
ADVANCE THE WORLD.
Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward.
Join us and, together, we’ll advance your career.
THE ROLE:
The DFT team furthers and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development.
THE PERSON:
You have a passion for modern, digital design, and DFT in general.
You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones.
You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.

Collected minimum qualification

Benefits offered are described:  <a href="https://www.amd.com/en/corporate/careers/benefits.html" target="_blank" rel="noopener">AMD benefits at a glance</a>. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD’s “Responsible AI Policy” is available <a href="https://www.amd.com/en/legal/responsible-ai-use-policy.html" target="_blank" rel="noopener">here.</a> This posting is for an existing vacancy.

Collected preferred qualification

<span style="margin: 0px; padding: 0px;" data-ccp-charstyle="normaltextrun" data-ccp-charstyle-defn="{"ObjectId":"75ee5cbf-7016-4753-9550-8bbf976473cd|105","ClassId":1073872969,"Properties":[469775450,"normaltextrun",201340122,"1",134233614,"true",469778129,"normaltextrun",335572020,"1",469778324,"Default Paragraph Font"]}">LEAD DFT DV ENGINEER<span style="margin: 0px; padding: 0px;" data-ccp-charstyle="eop" data-ccp-charstyle-defn="{"ObjectId":"75ee5cbf-7016-4753-9550-8bbf976473cd|106","ClassId":1073872969,"Properties":[469775450,"eop",201340122,"1",134233614,"true",469778129,"eop",335572020,"1",469778324,"Default Paragraph Font"]}"> <span style="margin: 0px; padding: 0px; font-family: Arial, Arial_EmbeddedFont, Arial_MSFontService, sans-serif;" data-ccp-props="{"134233117":false,"134233118":false,"201341983":0,"335551550":2,"335551620":2,"335559738":0,"335559739":0,"335559740":240}">  <span style="margin: 0px; padding: 0px; font-family: Arial, Arial_EmbeddedFont, Arial_MSFontService, sans-serif;" data-ccp-props="{"134233117":false,"134233118":false,"201341983":0,"335559738":0,"335559739":0,"335559740":240}"> THE ROLE: We are looking for an adaptive, self-motivative DFT engineer to join our growing team. As a key contributor, you will be part of a leading team to drive and improve AMD's abilities to deliver the highest quality, industry-leading technologies to market. The DFT team furthers and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development.  THE PERSON: You have a passion for modern, digital design, and DFT in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.  PREFERRED EXPERIENCE: <ul style="direction: ltr; unicode-bidi: embed; margin-top: 0in; margin-bottom: 0in;" type="disc"><li style="margin-left: 0in;">Good understanding and experience in DFT clocking and topology covering MBIST, JTAG verification, scan dump, understanding on ICL/PDL, debug scenarios like clock observation and analog observation, BScan, HSIO tests experience </li></ul><ul style="margin-top: 0in;"><li style="margin-left: 0in;">Experience in multi die scenarios verification is preferable</li><li style="margin-left: 0in;">Work closely with design /Arch team to prepare test list and complete the verification with all planned tests</li><li style="margin-left: 0in;">Develop scalable verification platform in System Verilog / UVM. Able to guide team in writing assertions and checkers.</li><li style="margin-left: 0in;">Be responsible for a comprehensive verification plan and drive the implementation of verification tests</li><li style="margin-left: 0in;">Responsible for SCAN, MBIST and JTAG verification</li></ul> ACADEMIC CREDENTIALS: Bachelors degree w/7+ years or Masters degree w/5+ years in Electronics engineering/Electrical Engineering #LI-AB1

Collected experience requirement

7+ years