FCT PD lead

AMD · Bangalore

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Collected role description

Role overview

FCT PD lead at AMD

Develop, validate, and maintain block, subsystem, and SoC-level timing constraints (SDC).

Responsibilities

Perform comprehensive timing analysis and closure for full-chip and partition-level designs.
Analyze setup, hold, SI, OCV, AOCV, POCV, CDC-related, and mode-specific timing violations.
Drive timing convergence across multiple corners, modes, and milestone releases.
Debug timing issues originating from RTL, constraints, clock architecture, physical implementation, and ECO changes.
Own timing signoff readiness and ensure timing quality across all project deliverables.
Collaborate with Tile PnR, Clocking, DFT, Integration, and RTL teams to resolve critical timing bottlenecks.
Develop timing automation, QoR dashboards, and methodology improvements to improve closure efficiency.
Support customer timing reviews, signoff audits, and tapeout readiness activities.
Mentor junior engineers and provide technical guidance on timing methodologies and best practices.

Required qualifications

Bachelor's or Master's degree in Electrical Engineering, Electronics, VLSI, Computer Engineering, or related field.
7 to 10 years of experience in STA, Timing Closure, Constraints Development, or Physical Design.
Strong understanding of STA concepts including setup, hold, recovery, removal, SI, OCV, AOCV, and POCV.
Hands-on experience developing and validating SDC constraints.
Proficiency with Synopsys PrimeTime and timing signoff methodologies.
Strong understanding of clocking architectures, timing exceptions, and CDC interactions.
Experience debugging timing violations and driving closure across multiple corners and modes.
Proficiency in Tcl, Python, Perl, or Shell scripting.
Strong analytical, problem-solving, and communication skills.
Minimum qualification: Benefits offered are described: AMD benefits at a glance . AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.

Preferred qualifications and skills

Experience driving full-chip timing closure for large CPU, GPU, AI/ML, networking, or datacenter SoCs.
Expertise in constraint quality checks, timing signoff reviews, and correlation methodologies.
Knowledge of clock-domain crossings, asynchronous interfaces, and timing exception verification.
Experience with PrimeTime, PrimeTime-SI, Tempus, Fusion Compiler, or equivalent EDA tools.
Familiarity with low-power timing methodologies, UPF flows, and advanced-node signoff requirements.
Experience supporting tapeouts at 5nm, 4nm, 3nm, or newer process technologies.
Proven track record of independently driving timing convergence for critical project milestones.
Experience developing automation, AI-assisted timing analysis flows, and productivity-enhancing methodologies.
Success Profile for an MTS FCT Engineer
Independently owns timing closure for major SoC partitions or full-chip domains.
Recognized as a constraints and STA expert within the project team.
Drives timing convergence with minimal supervision.
Identifies and resolves complex timing issues across RTL, Clocking, DFT, and Physical Design.
Contributes to methodology improvements that improve timing closure efficiency, quality, and scalability.
#LI-BM2
Benefits offered are described: AMD benefits at a glance .
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services.
AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.
We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.
AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.

Employment details

Location: Bangalore [India]

About the employer

At AMD, we believe technology has the power to solve the world’s most important challenges.

Benefits

From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future.

Additional role details

ADVANCE YOUR CAREER.
ADVANCE THE WORLD.
Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward.
Join us and, together, we’ll advance your career.
MTS Silicon Design Engineer – Constraints & Full-Chip Timing (FCT)
Role Summary
Responsible for developing, validating, and maintaining timing constraints and driving full-chip timing convergence for complex SoCs.
The engineer will own SDC methodology, timing signoff quality, cross-domain timing closure, and collaborate with RTL, Architecture, Tile PnR, Clocking, DFT, and Full-Chip teams to achieve timing signoff targets across all project milestones.

Collected minimum qualification

Benefits offered are described:  <a href="https://www.amd.com/en/corporate/careers/benefits.html" target="_blank" rel="noopener">AMD benefits at a glance</a>. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD’s “Responsible AI Policy” is available <a href="https://www.amd.com/en/legal/responsible-ai-use-policy.html" target="_blank" rel="noopener">here.</a> This posting is for an existing vacancy.

Collected preferred qualification

MTS Silicon Design Engineer – Constraints & Full-Chip Timing (FCT)Role SummaryResponsible for developing, validating, and maintaining timing constraints and driving full-chip timing convergence for complex SoCs. The engineer will own SDC methodology, timing signoff quality, cross-domain timing closure, and collaborate with RTL, Architecture, Tile PnR, Clocking, DFT, and Full-Chip teams to achieve timing signoff targets across all project milestones.Key Responsibilities<ul style="margin-top: 0in;"><li>Develop, validate, and maintain block, subsystem, and SoC-level timing constraints (SDC).</li><li>Perform comprehensive timing analysis and closure for full-chip and partition-level designs.</li><li>Analyze setup, hold, SI, OCV, AOCV, POCV, CDC-related, and mode-specific timing violations.</li><li>Drive timing convergence across multiple corners, modes, and milestone releases.</li><li>Debug timing issues originating from RTL, constraints, clock architecture, physical implementation, and ECO changes.</li><li>Own timing signoff readiness and ensure timing quality across all project deliverables.</li><li>Collaborate with Tile PnR, Clocking, DFT, Integration, and RTL teams to resolve critical timing bottlenecks.</li><li>Develop timing automation, QoR dashboards, and methodology improvements to improve closure efficiency.</li><li>Support customer timing reviews, signoff audits, and tapeout readiness activities.</li><li>Mentor junior engineers and provide technical guidance on timing methodologies and best practices.</li></ul>Required Qualifications<ul style="margin-top: 0in;"><li>Bachelor's or Master's degree in Electrical Engineering, Electronics, VLSI, Computer Engineering, or related field.</li><li>7 to 10 years of experience in STA, Timing Closure, Constraints Development, or Physical Design.</li><li>Strong understanding of STA concepts including setup, hold, recovery, removal, SI, OCV, AOCV, and POCV.</li><li>Hands-on experience developing and validating SDC constraints.</li><li>Proficiency with Synopsys PrimeTime and timing signoff methodologies.</li><li>Strong understanding of clocking architectures, timing exceptions, and CDC interactions.</li><li>Experience debugging timing violations and driving closure across multiple corners and modes.</li><li>Proficiency in Tcl, Python, Perl, or Shell scripting.</li><li>Strong analytical, problem-solving, and communication skills.</li></ul>Preferred Experience<ul style="margin-top: 0in;"><li>Experience driving full-chip timing closure for large CPU, GPU, AI/ML, networking, or datacenter SoCs.</li><li>Expertise in constraint quality checks, timing signoff reviews, and correlation methodologies.</li><li>Knowledge of clock-domain crossings, asynchronous interfaces, and timing exception verification.</li><li>Experience with PrimeTime, PrimeTime-SI, Tempus, Fusion Compiler, or equivalent EDA tools.</li><li>Familiarity with low-power timing methodologies, UPF flows, and advanced-node signoff requirements.</li><li>Experience supporting tapeouts at 5nm, 4nm, 3nm, or newer process technologies.</li><li>Proven track record of independently driving timing convergence for critical project milestones.</li><li>Experience developing automation, AI-assisted timing analysis flows, and productivity-enhancing methodologies.</li></ul>Success Profile for an MTS FCT Engineer<ul style="margin-top: 0in;"><li>Independently owns timing closure for major SoC partitions or full-chip domains.</li><li>Recognized as a constraints and STA expert within the project team.</li><li>Drives timing convergence with minimal supervision.</li><li>Identifies and resolves complex timing issues across RTL, Clocking, DFT, and Physical Design.</li><li>Contributes to methodology improvements that improve timing closure efficiency, quality, and scalability.</li></ul> #LI-BM2

Collected experience requirement

7-10 years