Post‑Silicon SoC & System‑Level Validation Engineer

AMD · Bangalore

Collected role description

Role overview

Post‑Silicon SoC & System‑Level Validation Engineer at AMD

This role focuses on validating end‑to‑end system behavior , ensuring that multiple SoC subsystems interact correctly under real customer and system‑level use cases .

Responsibilities

Own SoC‑level post‑silicon validation , focusing on interaction between multiple subsystems rather than isolated IP testing.
Validate end‑to‑end system flows involving CPU cores, on‑chip memories, NoC/interconnect, IOs, power management, and firmware.
Ensure correct behavior across boot, runtime, stress, error, and recovery scenarios at the SoC level.
Develop validation test cases based on customer use cases (boot flows, IO usage, stress, concurrency, power transitions) into executable validation plans.
Debug & root cause analysis: Perform deep SoC‑level debug to isolate failures across hardware, firmware, and system software boundaries
Lab execution & characterization: Use engineering lab equipment (oscilloscopes, protocol analyzers, signal generators, etc.) to validate and debug functional behavior
Documentation & reporting: Produce clear test plans, execution reports, failure analysis summaries, and status updates; track bugs/issues to closure

Required qualifications

Experience in pre‑silicon and/or post‑silicon SoC validation , with strong ownership in post‑silicon execution.
Strong understanding of SoC architecture and subsystem interactions .
Experience validating system‑level use cases and customer‑driven scenarios .
Familiarity with debug tools , system logs, traces, and lab‑based validation setups
Strong understanding of SoC boot flows, firmware, and HW/SW interaction .
Lab proficiency: Extensive experience using lab equipment such as oscilloscopes, protocol analyzers, signal generators, etc.
Minimum qualification: Benefits offered are described: AMD benefits at a glance . AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.

Preferred qualifications and skills

Experience with emulation platforms (Palladium, Protium, Zebu) for pre‑silicon or early validation.
Exposure to NoC fabrics, power management, clock/reset architecture, and system controllers .
Familiarity with system software stacks (bootloader, Linux, RTOS) and their interaction with silicon.
Hands on experience using AI tools
#LI-NS2
Benefits offered are described: AMD benefits at a glance .
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services.
AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.
We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.
AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.

Employment details

Location: Bangalore [India]

About the employer

WHAT YOU DO AT AMD CHANGES EVERYTHING
When you join AMD, you’ll discover the real differentiator is our culture.

Additional role details

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems.
Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary.
We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives.
Join us as we shape the future of AI and beyond. Together, we advance your career.

Collected minimum qualification

Benefits offered are described:  <a href="https://www.amd.com/en/corporate/careers/benefits.html" target="_blank" rel="noopener">AMD benefits at a glance</a>. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD’s “Responsible AI Policy” is available <a href="https://www.amd.com/en/legal/responsible-ai-use-policy.html" target="_blank" rel="noopener">here.</a> This posting is for an existing vacancy.

Collected preferred qualification

Role Overview :This role focuses on validating end‑to‑end system behavior, ensuring that multiple SoC subsystems interact correctly under real customer and system‑level use cases.  KEY RESPONSIBILITIES:  <ul style="margin-top: 0in; margin-bottom: 0in;" type="disc"><li style="margin-top: 0in; margin-right: 0in; margin-bottom: 0in; font-size: 12pt; font-family: arial, helvetica, sans-serif;">Own SoC‑level post‑silicon validation, focusing on interaction between multiple subsystems rather than isolated IP testing.</li><li style="margin-top: 0in; margin-right: 0in; margin-bottom: 0in; font-size: 12pt; font-family: arial, helvetica, sans-serif;">Validate end‑to‑end system flows involving CPU cores, on‑chip memories, NoC/interconnect, IOs, power management, and firmware.</li><li style="margin-top: 0in; margin-right: 0in; margin-bottom: 0in; font-size: 12pt; font-family: arial, helvetica, sans-serif;">Ensure correct behavior across boot, runtime, stress, error, and recovery scenarios at the SoC level.</li></ul><ul style="margin-top: 0in; margin-bottom: 0in;" type="disc"><li style="margin-top: 0in; margin-right: 0in; margin-bottom: 0in; font-size: 12pt; font-family: arial, helvetica, sans-serif;">Develop validation test cases based on customer use cases  (boot flows, IO usage, stress, concurrency, power transitions) into executable validation plans.</li><li style="margin-top: 0in; margin-right: 0in; margin-bottom: 0in; font-size: 12pt; font-family: arial, helvetica, sans-serif;">Debug & root cause analysis: Perform deep SoC‑level debug to isolate failures across hardware, firmware, and system software boundaries</li><li style="margin-top: 0in; margin-right: 0in; margin-bottom: 0in; font-size: 12pt; font-family: arial, helvetica, sans-serif;">Lab execution & characterization: Use engineering lab equipment (oscilloscopes, protocol analyzers, signal generators, etc.) to validate and debug functional behavior</li><li style="margin-top: 0in; margin-right: 0in; margin-bottom: 0in; font-size: 12pt; font-family: arial, helvetica, sans-serif;">Documentation & reporting: Produce clear test plans, execution reports, failure analysis summaries, and status updates; track bugs/issues to closure</li></ul> QUALIFICATIONS:<ul style="margin-top: 0in; margin-bottom: 0in;" type="disc"><li style="margin-top: 0in; margin-right: 0in; margin-bottom: 0in; font-size: 12pt; font-family: arial, helvetica, sans-serif;">Experience in pre‑silicon and/or post‑silicon SoC validation, with strong ownership in post‑silicon execution.</li><li style="margin-top: 0in; margin-right: 0in; margin-bottom: 0in; font-size: 12pt; font-family: arial, helvetica, sans-serif;">Strong understanding of SoC architecture and subsystem interactions.</li><li style="margin-top: 0in; margin-right: 0in; margin-bottom: 0in; font-size: 12pt; font-family: arial, helvetica, sans-serif;">Experience validating system‑level use cases and customer‑driven scenarios.</li></ul><ul style="margin-top: 0in; margin-bottom: 0in;" type="disc"><li style="margin-top: 0in; margin-right: 0in; margin-bottom: 0in; font-size: 12pt; font-family: arial, helvetica, sans-serif;">Familiarity with debug tools, system logs, traces, and lab‑based validation setups</li><li style="margin-top: 0in; margin-right: 0in; margin-bottom: 0in; font-size: 12pt; font-family: arial, helvetica, sans-serif;">Strong understanding of SoC boot flows, firmware, and HW/SW interaction.</li><li style="margin-top: 0in; margin-right: 0in; margin-bottom: 0in; font-size: 12pt; font-family: arial, helvetica, sans-serif;">Lab proficiency: Extensive experience using lab equipment such as oscilloscopes, protocol analyzers, signal generators, etc.</li></ul> Preferred Qualifications :<ul style="margin-top: 0in; margin-bottom: 0in;" type="disc"><li style="margin-top: 0in; margin-right: 0in; margin-bottom: 0in; font-size: 12pt; font-family: arial, helvetica, sans-serif;">Experience with emulation platforms (Palladium, Protium, Zebu) for pre‑silicon or early validation.</li></ul><ul style="margin-top: 0in; margin-bottom: 0in;" type="disc"><li style="margin-top: 0in; margin-right: 0in; margin-bottom: 0in; font-size: 12pt; font-family: arial, helvetica, sans-serif;">Exposure to NoC fabrics, power management, clock/reset architecture, and system controllers. </li></ul><ul style="margin-top: 0in; margin-bottom: 0in;" type="disc"><li style="margin-top: 0in; margin-right: 0in; margin-bottom: 0in; font-size: 12pt; font-family: arial, helvetica, sans-serif;">Familiarity with system software stacks (bootloader, Linux, RTOS) and their interaction with silicon.</li><li style="margin-top: 0in; margin-right: 0in; margin-bottom: 0in; font-size: 12pt; font-family: arial, helvetica, sans-serif;">Hands on experience using AI tools</li></ul>  #LI-NS2