Manager - Design Engineering

<p style="margin:0px;padding:0px;border:0px;font-family:inherit;vertical-align:baseline;">🔹 Key Responsibilities:</p><p style="margin:0px;padding:0px;border:0px;font-family:inherit;vertical-align:baseline;">

• Design and develop synthesizable RTL using Verilog/System Verilog</p><p style="margin:0px;padding:0px;border:0px;font-family:inherit;vertical-align:baseline;">
• Translate architecture specifications into micro-architecture and RTL implementation</p><p style="margin:0px;padding:0px;border:0px;font-family:inherit;vertical-align:baseline;">
• Develop high-performance and low-power digital design blocks</p><p style="margin:0px;padding:0px;border:0px;font-family:inherit;vertical-align:baseline;">
• Work closely with verification teams for functional validation and debug</p><p style="margin:0px;padding:0px;border:0px;font-family:inherit;vertical-align:baseline;">
• Perform design reviews and ensure coding quality and design guidelines</p><p style="margin:0px;padding:0px;border:0px;font-family:inherit;vertical-align:baseline;">
• Collaborate with physical design teams to meet timing, power, and area requirements</p><p style="margin:0px;padding:0px;border:0px;font-family:inherit;vertical-align:baseline;">
• Debug RTL issues and support silicon bring-up when required</p><p style="margin:0px;padding:0px;border:0px;font-family:inherit;vertical-align:baseline;"><br /></p><p style="margin:0px;padding:0px;border:0px;font-family:inherit;vertical-align:baseline;">🔹 Required Skills:</p><p style="margin:0px;padding:0px;border:0px;font-family:inherit;vertical-align:baseline;">
• Strong expertise in Verilog and System Verilog</p><p style="margin:0px;padding:0px;border:0px;font-family:inherit;vertical-align:baseline;">
• Solid understanding of digital design fundamentals and computer architecture</p><p style="margin:0px;padding:0px;border:0px;font-family:inherit;vertical-align:baseline;">
• Experience with AMBA protocols such as AXI, AHB, and APB</p><p style="margin:0px;padding:0px;border:0px;font-family:inherit;vertical-align:baseline;">
• Knowledge of synthesis, timing closure, and low-power design techniques</p><p style="margin:0px;padding:0px;border:0px;font-family:inherit;vertical-align:baseline;">
• Familiarity with simulation and debugging tools</p><p style="margin:0px;padding:0px;border:0px;font-family:inherit;vertical-align:baseline;">
• Experience working in ASIC/SoC design environments</p><p style="margin:0px;padding:0px;border:0px;font-family:inherit;vertical-align:baseline;"><br /></p><p style="margin:0px;padding:0px;border:0px;font-family:inherit;vertical-align:baseline;">🔹 Preferred Qualifications:</p><p style="margin:0px;padding:0px;border:0px;font-family:inherit;vertical-align:baseline;">
• Strong debugging and problem-solving skills</p><p style="margin:0px;padding:0px;border:0px;font-family:inherit;vertical-align:baseline;">
• Bachelor’s or master’s degree in electrical engineering, Computer Engineering, or a related field.</p><p style="margin:0px;padding:0px;border:0px;font-family:inherit;vertical-align:baseline;">
• Strong understanding of digital logic design principles.</p><p style="margin:0px;padding:0px;border:0px;font-family:inherit;vertical-align:baseline;"><br style="color:rgba(0,0,0,0.9);font-family:'system-ui', '-apple-system', BlinkMacSystemFont, 'Segoe UI', Roboto, Ubuntu, Oxygen, Cantarell, 'Fira Sans', 'Droid Sans', 'Helvetica Neue', Arial, sans-serif, 'Apple Color Emoji', 'Segoe UI Emoji', 'Segoe UI Symbol';white-space:pre-wrap;" /></p>