ASIC DFT DV Engineer || System Verilog, UVM || JTAG, MBIST || Exp : 8+ years

Role overview

ASIC DFT DV Engineer || System Verilog, UVM || JTAG, MBIST || Exp : 8+ years at Cisco

Responsibilities

• Collaborate with RTL and physical design teams, develop test benches, and support ATE screening and diagnostics.

Employment details

• Location: Bangalore [India], Hyderabad [Telangāna] [India]

Additional role details

• Seeking an ASIC DFT DV Engineer to drive high-quality DFT verification and test planning for advanced networking hardware.
• Ideal for candidates with extensive experience in System Verilog, DFT, and test strategy.