ASIC Engineering Digital Designer/ Leader ( digital design, FSM, CPU sub-systems, complex SOCs | 8-12 Years | Pune/ Bangalore)

Role overview

ASIC Engineering Digital Designer/ Leader ( digital design, FSM, CPU sub-systems, complex SOCs | 8-12 Years | Pune/ Bangalore) at Cisco

Responsibilities

• Lead the full ASIC lifecycle, collaborate with cross-functional teams, and drive technical strategy.

Employment details

• Location: Pune [India], Bangalore [India]

Additional role details

• Seeking a senior-level ASIC Engineering Digital Designer/Leader to provide technical leadership in the development of digital logic for silicon photonics, focusing on high-speed optical interconnects.
• Ideal for candidates with extensive experience in digital design and ASIC/SoC design.