Leader/Manager, ASIC Design Verification Engineering || Verilog, UVM, TestBench, Technical Leadership, Hardware Emulation, SOC || Exp - 15 + years

Role overview

Leader/Manager, ASIC Design Verification Engineering || Verilog, UVM, TestBench, Technical Leadership, Hardware Emulation, SOC || Exp - 15 + years at Cisco

Employment details

• Location: Bangalore [India]

About the employer

• We are recruiting an ASIC Design Verification Engineering Leader to drive high-performance ASIC design verification for Cisco's enterprise platforms.

Additional role details

• Lead teams in defining and verifying ASICs, collaborate cross-functionally, and ensure quality delivery.
• Ideal for experienced ASIC engineers with strong technical leadership and expertise in UVM, C++, and ASIC development.