DFT Engineering Technical Lead || ATPG, SCAN, JTAG, MBIST, TestMax, Tessent || Exp - 10+ years

Role overview

DFT Engineering Technical Lead || ATPG, SCAN, JTAG, MBIST, TestMax, Tessent || Exp - 10+ years at Cisco

Responsibilities

• Lead innovation in DFT IP development and collaborate with cross-functional teams to integrate testability.

Employment details

• Location: Bangalore [India], Chennai [India], Hyderabad [Telangāna] [India]

Additional role details

• Join our team as a DFT Engineering Technical Lead, driving the implementation of Hardware Design-for-Test features for advanced networking hardware.
• Ideal for experienced engineers with deep expertise in DFT, test, and silicon engineering.