ASIC Design Verification Engineer | UVM | Exp 8+ Years

Role overview

ASIC Design Verification Engineer | UVM | Exp 8+ Years at Cisco

Employment details

• Location: Bangalore [India]

About the employer

• We are recruiting a ASIC Design Verification Engineer to define, design, and verify ASIC and subsystems for Cisco platforms.

Additional role details

• You will architect and develop DV infrastructure, develop test plans, and ensure RTL quality.
• Ideal for candidates with significant ASIC verification experience and expertise in UVM/System Verilog.