Design Verification Manager, Silicon
Google · Bangalore
Collected role description
Role overview
Design Verification Manager, Silicon at Google
Required qualifications
- Minimum qualification: Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience.; 15 years of experience in front-end design or design verification.; Experience in power-aware verification methodologies.; Experience in fabric and interconnect architectures and cache coherency protocols.
Preferred qualifications and skills
- Preferred qualification: Master's degree in Electrical Engineering or Computer Science or equivalent practical experience.; Experience in verification of high-bandwidth memory subsystems (DDR5, LPDDR5, HBM) including physical layer (PHY) training, memory controllers, and JEDEC compliance.; Experience directly managing high-performing engineering teams with a proven track record of successfully delivering complex, production-grade SoCs.; Experience in SoC-level verification and strong design verification (DV) fundamentals using universal verification methodology (UVM)-based environments, and with with pre-silicon emulation platforms and hardware accelerators (e.g., SimXL, formal verification, or portable stimulus standard/PSS).; Excellent programming skills in SystemVerilog, Verilog, and scripting languages like Python or Perl.
Employment details
- Location: Bengaluru [Karnataka] [India]
Application details
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About the employer
- Google is proud to be an equal opportunity and affirmative action employer.
- Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting.
- Please do not forward resumes to our jobs alias, Google employees, or any other organization location.
Additional role details
- We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents-to-be, criminal histories consistent with legal requirements, or any other basis protected by law.
- See also Google's EEO Policy , Know your rights: workplace discrimination is illegal , Belonging at Google , and How we hire .
- If you have a need that requires accommodation, please let us know by completing our Accommodations for Applicants form .
- To all recruitment agencies: Google does not accept agency resumes.
- Google is not responsible for any fees related to unsolicited resumes.
- Equity is granted exclusively and discretionarily by Alphabet Inc. on the basis of an agreement concluded between you and Alphabet Inc.
- Alphabet Inc. is your sole contractual partner with respect to equity grants.
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- They have no impact on statutory payments.
- Current or past grants do not confer an acquired right.
Collected minimum qualification
Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience.; 15 years of experience in front-end design or design verification.; Experience in power-aware verification methodologies.; Experience in fabric and interconnect architectures and cache coherency protocols.
Collected preferred qualification
Master's degree in Electrical Engineering or Computer Science or equivalent practical experience.; Experience in verification of high-bandwidth memory subsystems (DDR5, LPDDR5, HBM) including physical layer (PHY) training, memory controllers, and JEDEC compliance.; Experience directly managing high-performing engineering teams with a proven track record of successfully delivering complex, production-grade SoCs.; Experience in SoC-level verification and strong design verification (DV) fundamentals using universal verification methodology (UVM)-based environments, and with with pre-silicon emulation platforms and hardware accelerators (e.g., SimXL, formal verification, or portable stimulus standard/PSS).; Excellent programming skills in SystemVerilog, Verilog, and scripting languages like Python or Perl.
Collected experience requirement
15 years of experience in front-end design or design verification.