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Senior Silicon DFT Micro Architecture Engineer, Google Cloud

Google · Bangalore

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Collected role description

Role overview

Senior Silicon DFT Micro Architecture Engineer, Google Cloud at Google

Required qualifications

  • Minimum qualification: Bachelor's degree in Electrical Engineering or a related field, or equivalent practical experience.; 8 years of experience in the implementation and validation of DFT technologies.; Experience with multiple projects in DFT design and verification, DFT specification, definition, architecture, and insertion.; Experience with DFT techniques and tools, ASIC DFT synthesis, simulation, and verification flow.; Experience in leading DFT activities throughout an ASIC development flow.

Preferred qualifications and skills

  • Preferred qualification: Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science or a related field.; Experience in IP integration (e.g., memories, test controllers, Test Access Point (TAP), and DFT for Multi die SoCs).; Experience in fault modeling.; Experience in SoC cycles, silicon bringup, and silicon debug activities.

Employment details

  • Location: Bengaluru [Karnataka] [India]

Application details

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About the employer

  • Google is proud to be an equal opportunity and affirmative action employer.
  • Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting.
  • Please do not forward resumes to our jobs alias, Google employees, or any other organization location.

Additional role details

  • We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents-to-be, criminal histories consistent with legal requirements, or any other basis protected by law.
  • See also Google's EEO Policy , Know your rights: workplace discrimination is illegal , Belonging at Google , and How we hire .
  • If you have a need that requires accommodation, please let us know by completing our Accommodations for Applicants form .
  • To all recruitment agencies: Google does not accept agency resumes.
  • Google is not responsible for any fees related to unsolicited resumes.
  • Equity is granted exclusively and discretionarily by Alphabet Inc. on the basis of an agreement concluded between you and Alphabet Inc.
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  • They have no impact on statutory payments.
  • Current or past grants do not confer an acquired right.

Collected minimum qualification

Bachelor's degree in Electrical Engineering or a related field, or equivalent practical experience.; 8 years of experience in the implementation and validation of DFT technologies.; Experience with multiple projects in DFT design and verification, DFT specification, definition, architecture, and insertion.; Experience with DFT techniques and tools, ASIC DFT synthesis, simulation, and verification flow.; Experience in leading DFT activities throughout an ASIC development flow.

Collected preferred qualification

Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science or a related field.; Experience in IP integration (e.g., memories, test controllers, Test Access Point (TAP), and DFT for Multi die SoCs).; Experience in fault modeling.; Experience in SoC cycles, silicon bringup, and silicon debug activities.

Collected experience requirement

8 years of experience in the implementation and validation of DFT technologies.