Senior Silicon Engineer, HBM Memory Subsystem Design, Integration and Validation

Role overview

Senior Silicon Engineer, HBM Memory Subsystem Design, Integration and Validation at Google

Required qualifications

• Minimum qualification: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.; 10 years of experience in memory subsystem design, integration or verification.; Experience with DRAM protocols (HBM2e/HBM3/HBM4 or DDR/LPDDR4x/5/5X) including Joint Electron Device Engineering Council (JEDEC) timing, refresh and training sequences.; Experience with the DFI controller-to-PHY interface, leading a feature or IP block, and mentoring engineers.; Experience in SystemVerilog RTL, simulation and debug flows.

Preferred qualifications and skills

• Preferred qualification: Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.; Experience delivering configurable, reusable IP-parameterization, release packaging, integration guides and customer-facing documentation.; Experience integrating third-party controller and PHY IP (Rambus, Cadence/Synopsys class) into production silicon.; Experience with SECDED per pseudo-channel, Reed–Solomon symbol correction, error queues, lane/row repair, address-folded CRC.; Experience with UVM methodology and emulation-based pre-silicon validation, and familiarity with memory telemetry and Silicon Lifecycle Management (SLM) — per-pseudo-channel counters, link availability, continuous eye-opening monitors.

Employment details

• Location: Bengaluru [Karnataka] [India]

Application details

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About the employer

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Additional role details

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