Formal Verification Engineer

Role overview

Formal Verification Engineer at IBM

Responsibilities

• Lead formal verification efforts for complex processor/SoC/ASIC designs used in IBM server platforms.
• Create high-quality test scenarios and properties to ensure comprehensive functional correctness.
• Drive quality metrics, ensure signoff readiness, and deliver production-quality designs. 5-7 years of relevant industry experience in semiconductor design/verification.

Employment details

• Location: Bangalore [India]

Application details

• Apply IBM formal verification tools, methodologies, and best practices to achieve efficient verification closure.

About the employer

• At IBM Infrastructure & Technology, we design and operate the systems that keep the world running.
• Our teams ensure the performance, security, and scalability that clients and industries depend on every day.
• At IBM, we are driven by innovation and excellence in system design.
• Experience with IBM internal tools/flows (or equivalent industry-standard formal tools).

Additional role details

• From high-resiliency mainframes and hybrid cloud platforms to networking, automation, and site reliability.
• Working in Infrastructure & Technology means tackling complex challenges with curiosity and collaboration.
• You’ll work with diverse technologies and colleagues worldwide to deliver resilient, future-ready solutions that power innovation.
• With continuous learning, career growth, and a supportive culture, IBM provides the opportunities to build expertise and shape the infrastructure that drives progress.
• As a Formal Verification Lead, you will contribute to the verification of next-generation IBM server-class processors, SoCs, and ASICs, ensuring delivery of high-quality, reliable hardware solutions.
• Define and drive verification strategy, including property development, proof planning, and coverage closure.
• Develop and maintain scalable formal verification environments, testbenches, and reusable verification components.
• Collaborate closely with design, architecture, and validation teams to debug and resolve logic/design issues.
• Proven experience in formal and/or functional verification, with demonstrated execution on logic block verification.
• Strong knowledge of formal verification methodologies and tools.
• Good understanding of HDLs (Verilog, VHDL, SystemVerilog) and assertion-based verification (SVA).
• Experience in developing verification environments/testbenches, debugging failures, and triaging issues.
• Strong programming skills in Python (or equivalent scripting languages).
• Solid understanding of processor/core micro-architecture.
• Ability to collaborate effectively across cross-functional teams.
• Exposure to high-performance processor or server-class SoC verification.
• Prior experience in leading verification efforts or mentoring engineers.
• Proven ability to drive verification coverage closure and ensure signoff readiness.
• Experience in leading verification teams and delivering across milestones.
• Ability to handle complex verification scenarios and contribute to high-level design discussions.
• Strong communication skills with the ability to work effectively in a global, cross-functional team environment.
• Demonstrated track record of technical leadership and team mentorship.
• Strong debugging, analytical, and problem-solving capabilities.
• India Infrastructure & Technology Hybrid Professional Bangalore, IN Bangalore (0063) IBM India Private Limited Communication Debugging Design Engineering Formal Verification Functional Verification Mentoring Computer Programming Python Readiness SystemVerilog Technical Leadership Very High Speed Integrated Circuit Program Hardware Description Language Verilog Scripting languages System-on-a-chip Verification Hardware Description Language