Design Verification Engineer- Display Interface Protocol Specialist

Role overview

Design Verification Engineer- Display Interface Protocol Specialist at MediaTek

Develop and implement comprehensive verification plans for DP/eDP and DP Tunnelling over USB4 IP and Subsystems.

Responsibilities

• Create and maintain testbenches using System Verilog and UVM methodology.
• Perform functional verification of RTL designs, including simulation, debugging, and coverage analysis.
• Collaborate with designers and other cross-functional teams to understand design specifications and requirements for IP and subsystems.
• Identify and resolve design and verification issues, ensuring high-quality and robust designs.
• Generate and analyze verification metrics to track progress and ensure coverage goals are met.
• Participate in design and verification reviews, providing technical expertise and insights.
• Stay updated with the latest verification technologies and methodologies and apply them to improve verification efficiency and effectiveness.
• Mentor junior verification engineers and provide technical guidance.

Required qualifications

• More than 4 Years Work Expe.
• We are seeking a highly skilled Design Verification Engineer with more than 5 years of experience, specializing in Display Interface protocols – specifically Display Port (DP/eDP) IP and subsystem verification, to join our innovative team.
• The ideal candidate will have a strong background in verification methodologies, expertise in System Verilog (SV) programming & UVM Methodology, excellent problem-solving skills, and the ability to work collaboratively in a fast-paced environment.

Employment details

• Location: Bangalore [India]

Additional role details

• Category: Chip Design