Senior Principal Verification Engineer

Role overview

Senior Principal Verification Engineer at onsemi India

We are seeking an experienced Senior Principal ASIC/SoC Verification Engineer to join our dynamic and fast‑paced engineering team.

Responsibilities

• Drive verification closure through functional, code, and assertion coverage , ensuring high‑quality deliverables.
• Build and integrate reusable Verification IP (VIP) and scalable verification components.
• Collaborate with internal teams and third‑party VIP providers to ensure seamless integration and compliance.
• Develop checkers, scoreboards, monitors, and coverage models to support robust verification. 3.
• Contribute to verification methodology improvements, automation, and flow optimization.
• Ensure adherence to best practices in UVM architecture, reuse, and maintainability 4.

Employment details

• Location: Bangalore [Karnataka] [India]

Application details

• Apply industry‑standard ASIC/SoC verification techniques including test planning, testbench creation, constrained‑random and directed stimulus, assertions, and coverage‑driven verification.
• Apply formal verification techniques where appropriate to complement simulation‑based verification. 5.

Additional role details

• In this role, you will be responsible for ensuring the functional correctness, robustness, and overall quality of our cutting‑edge semiconductor and SoC designs.
• If you thrive in a collaborative environment and enjoy solving complex technical challenges, this opportunity is an excellent fit. #LI-RG1 Responsibilities 1.
• Verification Planning and Execution Develop and execute comprehensive SoC/IP‑level verification plans aligned with design specifications and project goals.
• Perform SoC integration verification , validating interactions across subsystems, interfaces, and power/performance domains. 2.
• Testbench & Environment Development Architect, develop, and enhance SystemVerilog UVM/OVM‑based testbenches for IP and SoC‑level verification.
• Methodology, Flows & Best Practices Demonstrate strong understanding of ASIC/SoC design and verification methodologies , including constraint‑random verification and object‑oriented programming principles.
• Advanced Verification Skills Perform Gate‑Level Simulation (GLS) including SDF annotation, timing verification, and debug of post‑synthesis/post‑layout issues.
• Execute power‑aware verification using UPF/CPF, validating power modes, isolation, retention, and sequencing.
• Debug complex SoC‑level issues involving multiple clock domains, resets, and power states.
• Technical Skills Strong proficiency in SystemVerilog (UVM/OVM) and scripting languages such as Python, Perl, Tcl, C/C++, and Verilog PLI.
• Familiarity with standard protocols and interfaces (e.g., I2C, SPI, UART, AXI/AHB/APB ).
• Experience with simulation, debug, and coverage tools from major EDA vendors (Synopsys, Cadence, Siemens).
• Knowledge of CI/regression automation, version control, and workflow tools is a plus 6.
• Collaboration & Communication Work effectively with design, architecture, DV, validation, and firmware teams to drive verification to completion.
• Communicate technical concepts clearly through documentation, reviews, and cross‑functional discussions.
• Demonstrate initiative, strong analytical problem‑solving skills, and adaptability in a diverse team environment. #LI-RG1 Responsibilities 1.
• Demonstrate initiative, strong analytical problem‑solving skills, and adaptability in a diverse team environment. #LI-RG1