SOC Verification Engineer- SOC DDR, UMC

AMD · Bangalore

Collected role description

ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career. THE ROLE (SOC Verification Engineer: SOC DDR, UMC):<ul><li style="margin: 0cm 0cm 0cm 36.0pt;">Work on SOC level verification activities, the person will be responsible for bringup verification of LPDDR5, UMC at SOC. Work with testbench team to bringup required infra Structure to bring up testbench and simulation.</li><li style="margin: 0cm 0cm 0cm 36.0pt;">He will be responsible to coordinate with Design team for RTL delivery, work with design (IP, Subsystem, SOC) for RTL and TB collaterals and resolve issues.</li><li style="margin: 0cm 0cm 0cm 36.0pt;">He should have good understanding of LPDDR5, UMC.</li><li style="margin: 0cm 0cm 0cm 36.0pt;">He will be responsible to create TB collaterals for LPDDR5, UMC and phy bringup.</li></ul> THE PERSON:<ul><li style="margin: 0cm 0cm 0cm 36.0pt;">Engineer with strong self-driving ability.</li><li style="margin: 0cm 0cm 0cm 36.0pt;">Need excellent communication skills (both written and oral)</li><li style="margin: 0cm 0cm 0cm 36.0pt;">Strong problem-solving skills, go to person for SOC testbench, DDR verification, C/C++ Coding, UVM coding, Testcase coding, checkers and assertions.</li></ul> KEY RESPONSIBILITIES:<ul><li style="margin: 0cm 0cm 0cm 36.0pt;">DDR Simulation bringup (Has responsibility of TB, Testcase, coordination between design and dv team)</li><li style="margin: 0cm 0cm 0cm 36.0pt;">Memory verification is key responsibility.</li><li style="margin: 0cm 0cm 0cm 36.0pt;">Work with Memory architects to resolve issues seen in simulation.</li></ul> PREFERRED EXPERIENCE:<ul><li style="margin: 0cm 0cm 0cm 36.0pt;">Good understanding of LPDDR*, UMC, Nandflash, Nor Flash etc…</li><li style="margin: 0cm 0cm 0cm 36.0pt;">Expertise in IP, Subsystem and SOC Verification with specialization in NLP Simulation.</li><li style="margin: 0cm 0cm 0cm 36.0pt;">Strong hands-on experience in different SOC Verification activities, DDR Simulation, UVM, System Verilog, X86, C++, HW/SW co-verification, Scripting (phython) Test plan review, Debug/triage, Coverage, Strong Problem Solving, Automation and Debugging Skills, System bus protocol understanding including some of the common IPs like ACE, CHI, AXI, PCIe, DDR, memory controller etc.</li><li style="margin: 0cm 0cm 0cm 36.0pt;">Comfortable with design/verification tools and flows like VCS, Verdi, SOC Connectivity, SV assertions, HW-SW co-simulations, UPF/CPF flows etc. </li><li style="margin: 0cm 0cm 0cm 36.0pt;">Strong understanding of System integration, Make file flow, Verification Methodologies, Boot up sequence.</li><li style="margin: 0cm 0cm 0cm 36.0pt;">JIRA based project management is a plus. </li></ul> ACADEMIC CREDENTIALS:<ul><li style="margin: 0cm;">BE/B.Tech/ME/MTECH/MS or equivalent in ECE/EEE/CSE</li><li style="margin: 0cm;">8-12 years of strong DV experience in CLK, RST verification, NLP simulation, IP, Sub System & SOC Verification.</li></ul>#LI-AB1 Benefits offered are described: <a href="https://www.amd.com/en/corporate/careers/benefits.html" target="_blank" rel="noopener">AMD benefits at a glance</a>. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available <a href="https://www.amd.com/en/legal/responsible-ai-use-policy.html" target="_blank" rel="noopener">here.</a> This posting is for an existing vacancy.

Collected minimum qualification

Benefits offered are described:  <a href="https://www.amd.com/en/corporate/careers/benefits.html" target="_blank" rel="noopener">AMD benefits at a glance</a>. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD’s “Responsible AI Policy” is available <a href="https://www.amd.com/en/legal/responsible-ai-use-policy.html" target="_blank" rel="noopener">here.</a> This posting is for an existing vacancy.

Collected preferred qualification

THE ROLE (SOC Verification Engineer: SOC DDR, UMC):<ul><li style="margin: 0cm 0cm 0cm 36.0pt;">Work on SOC level verification activities, the person will be responsible for bringup verification of LPDDR5, UMC at SOC. Work with testbench team to bringup required infra Structure to bring up testbench and simulation.</li><li style="margin: 0cm 0cm 0cm 36.0pt;">He will be responsible to coordinate with Design team for RTL delivery, work with design (IP, Subsystem, SOC) for RTL and TB collaterals and resolve issues.</li><li style="margin: 0cm 0cm 0cm 36.0pt;">He should have good understanding of LPDDR5, UMC.</li><li style="margin: 0cm 0cm 0cm 36.0pt;">He will be responsible to create TB collaterals for LPDDR5, UMC and phy bringup.</li></ul> THE PERSON:<ul><li style="margin: 0cm 0cm 0cm 36.0pt;">Engineer with strong self-driving ability.</li><li style="margin: 0cm 0cm 0cm 36.0pt;">Need excellent communication skills (both written and oral)</li><li style="margin: 0cm 0cm 0cm 36.0pt;">Strong problem-solving skills, go to person for SOC testbench, DDR verification, C/C++ Coding, UVM coding, Testcase coding, checkers and assertions.</li></ul> KEY RESPONSIBILITIES:<ul><li style="margin: 0cm 0cm 0cm 36.0pt;">DDR Simulation bringup (Has responsibility of TB, Testcase, coordination between design and dv team)</li><li style="margin: 0cm 0cm 0cm 36.0pt;">Memory verification is key responsibility.</li><li style="margin: 0cm 0cm 0cm 36.0pt;">Work with Memory architects to resolve issues seen in simulation.</li></ul> PREFERRED EXPERIENCE:<ul><li style="margin: 0cm 0cm 0cm 36.0pt;">Good understanding of LPDDR*, UMC, Nandflash, Nor Flash etc…</li><li style="margin: 0cm 0cm 0cm 36.0pt;">Expertise in IP, Subsystem and SOC Verification with specialization in NLP Simulation.</li><li style="margin: 0cm 0cm 0cm 36.0pt;">Strong hands-on experience in different SOC Verification activities, DDR Simulation, UVM, System Verilog, X86, C++, HW/SW co-verification, Scripting (phython) Test plan review, Debug/triage, Coverage, Strong Problem Solving, Automation and Debugging Skills, System bus protocol understanding including some of the common IPs like ACE, CHI, AXI, PCIe, DDR, memory controller etc.</li><li style="margin: 0cm 0cm 0cm 36.0pt;">Comfortable with design/verification tools and flows like VCS, Verdi, SOC Connectivity, SV assertions, HW-SW co-simulations, UPF/CPF flows etc. </li><li style="margin: 0cm 0cm 0cm 36.0pt;">Strong understanding of System integration, Make file flow, Verification Methodologies, Boot up sequence.</li><li style="margin: 0cm 0cm 0cm 36.0pt;">JIRA based project management is a plus. </li></ul> ACADEMIC CREDENTIALS:<ul><li style="margin: 0cm;">BE/B.Tech/ME/MTECH/MS or equivalent in ECE/EEE/CSE</li><li style="margin: 0cm;">8-12 years of strong DV experience in CLK, RST verification, NLP simulation, IP, Sub System & SOC Verification.</li></ul>#LI-AB1

Collected experience requirement

8-12 years