DFT DV Lead

AMD · Bangalore

Collected role description

ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career. <span style="margin: 0px; padding: 0px;" data-ccp-charstyle="normaltextrun" data-ccp-charstyle-defn="{"ObjectId":"75ee5cbf-7016-4753-9550-8bbf976473cd|105","ClassId":1073872969,"Properties":[469775450,"normaltextrun",201340122,"1",134233614,"true",469778129,"normaltextrun",335572020,"1",469778324,"Default Paragraph Font"]}">MTS SILICON DESIGN ENGINEER<span style="margin: 0px; padding: 0px;" data-ccp-charstyle="eop" data-ccp-charstyle-defn="{"ObjectId":"75ee5cbf-7016-4753-9550-8bbf976473cd|106","ClassId":1073872969,"Properties":[469775450,"eop",201340122,"1",134233614,"true",469778129,"eop",335572020,"1",469778324,"Default Paragraph Font"]}"> <span style="margin: 0px; padding: 0px; font-family: Arial, Arial_EmbeddedFont, Arial_MSFontService, sans-serif;" data-ccp-props="{"134233117":false,"134233118":false,"201341983":0,"335551550":2,"335551620":2,"335559738":0,"335559739":0,"335559740":240}"> THE ROLE: The focus of this role is to plan, build, and execute the DFT verification of new and existing features for AMD’s Chiplets , resulting in no bugs in the final design. THE PERSON: As a DFx Verification Engineer, you will be primarily responsible for verification of architecture, design, and implementation of critical Design-for-Test (DFT) and Design-for-Debug (DFD) features for cutting edge AMD products and will be working with a team of design engineers from various global design locations on design-for-test (DFT) design and implementation, tool and methodology development, project execution and continuous improvement initiatives, this role provides an excellent growth opportunity for robust individuals looking to make a difference. KEY RESPONSIBILITIES: <ul type="disc"><li style="font-size: 10pt;">Collaborate with architects, design engineers, and firmware engineers to understand the new DFT features to be verified </li><li style="font-size: 10pt;">Estimate the time required to write the new feature tests and any required changes to the test environment </li><li style="font-size: 10pt;">Build the directed and random DFT verification tests </li><li style="font-size: 10pt;">Debug test failures to determine the root cause; work with RTL/DFT and firmware engineers to resolve design defects and correct any test issues </li><li style="font-size: 10pt;">Analyze and enhance legacy DFT test plans to accommodate new Design for Debug feature developments</li><li style="font-size: 10pt;">Write complex Perl scripts to update simulation files in a deterministic manner</li><li style="font-size: 10pt;">Recreate post-silicon failures in pre-silicon environment</li><li style="font-size: 10pt;">Conduct silicon debug and root cause analysis with minimal logging support</li><li style="font-size: 10pt;">Utilize JTAG protocols for debugging and validation</li></ul> PREFERRED EXPERIENCE: <ul type="disc"><li style="font-size: 10pt;">8+ years of experience in DFT Design Verification with strong debug capabilities</li><li style="font-size: 10pt;">Experienced with SystemVerilog/UVM testbench development for complex SoCs Including GLS & SDF verifications</li><li style="font-size: 10pt;">Advanced scripting skills (Python, Perl, etc.) for automation and testbench infrastructure</li><li style="font-size: 10pt;">Deep knowledge of digital design, RTL design, and verification flows</li><li style="font-size: 10pt;">Strong troubleshooting and analytical debugging skills with ability to debug without logs</li><li style="font-size: 10pt;"> Ability to quickly adapt to complex infrastructure environments</li><li style="font-size: 10pt;"> Excellent hands-on debug skills and attention to detail</li><li style="font-size: 10pt;">Proficient in debugging firmware and RTL code using simulation tools </li><li style="font-size: 10pt;">Exposure to leadership or mentorship is an asset </li></ul> ACADEMIC CREDENTIALS: <ul type="disc"><li style="font-size: 10pt;">Bachelors or Masters degree in computer engineering/Electrical Engineering </li></ul> #LI-PM2 Benefits offered are described: <a href="https://www.amd.com/en/corporate/careers/benefits.html" target="_blank" rel="noopener">AMD benefits at a glance</a>. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available <a href="https://www.amd.com/en/legal/responsible-ai-use-policy.html" target="_blank" rel="noopener">here.</a> This posting is for an existing vacancy.

Collected minimum qualification

Benefits offered are described:  <a href="https://www.amd.com/en/corporate/careers/benefits.html" target="_blank" rel="noopener">AMD benefits at a glance</a>. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD’s “Responsible AI Policy” is available <a href="https://www.amd.com/en/legal/responsible-ai-use-policy.html" target="_blank" rel="noopener">here.</a> This posting is for an existing vacancy.

Collected preferred qualification

<span style="margin: 0px; padding: 0px;" data-ccp-charstyle="normaltextrun" data-ccp-charstyle-defn="{"ObjectId":"75ee5cbf-7016-4753-9550-8bbf976473cd|105","ClassId":1073872969,"Properties":[469775450,"normaltextrun",201340122,"1",134233614,"true",469778129,"normaltextrun",335572020,"1",469778324,"Default Paragraph Font"]}">MTS SILICON DESIGN ENGINEER<span style="margin: 0px; padding: 0px;" data-ccp-charstyle="eop" data-ccp-charstyle-defn="{"ObjectId":"75ee5cbf-7016-4753-9550-8bbf976473cd|106","ClassId":1073872969,"Properties":[469775450,"eop",201340122,"1",134233614,"true",469778129,"eop",335572020,"1",469778324,"Default Paragraph Font"]}"> <span style="margin: 0px; padding: 0px; font-family: Arial, Arial_EmbeddedFont, Arial_MSFontService, sans-serif;" data-ccp-props="{"134233117":false,"134233118":false,"201341983":0,"335551550":2,"335551620":2,"335559738":0,"335559739":0,"335559740":240}">  THE ROLE: The focus of this role is to plan, build, and execute the DFT verification of new and existing features for AMD’s Chiplets , resulting in no bugs in the final design.      THE PERSON:  As a DFx Verification Engineer, you will be primarily responsible for verification of architecture, design, and implementation of critical Design-for-Test (DFT) and Design-for-Debug (DFD) features for cutting edge AMD products and will be working with a team of design engineers from various global design locations on design-for-test (DFT) design and implementation, tool and methodology development, project execution and continuous improvement initiatives, this role provides an excellent growth opportunity for robust individuals looking to make a difference.   KEY RESPONSIBILITIES:  <ul type="disc"><li style="font-size: 10pt;">Collaborate with architects, design engineers, and firmware engineers to understand the new DFT features to be verified </li><li style="font-size: 10pt;">Estimate the time required to write the new feature tests and any required changes to the test environment </li><li style="font-size: 10pt;">Build the directed and random DFT verification tests </li><li style="font-size: 10pt;">Debug test failures to determine the root cause; work with RTL/DFT and firmware engineers to resolve design defects and correct any test issues  </li><li style="font-size: 10pt;">Analyze and enhance legacy DFT test plans to accommodate new Design for Debug feature developments</li><li style="font-size: 10pt;">Write complex Perl scripts to update simulation files in a deterministic manner</li><li style="font-size: 10pt;">Recreate post-silicon failures in pre-silicon environment</li><li style="font-size: 10pt;">Conduct silicon debug and root cause analysis with minimal logging support</li><li style="font-size: 10pt;">Utilize JTAG protocols for debugging and validation</li></ul>   PREFERRED EXPERIENCE:  <ul type="disc"><li style="font-size: 10pt;">8+ years of experience in DFT Design Verification with strong debug capabilities</li><li style="font-size: 10pt;">Experienced with SystemVerilog/UVM testbench development for complex SoCs Including GLS & SDF verifications</li><li style="font-size: 10pt;">Advanced scripting skills (Python, Perl, etc.) for automation and testbench infrastructure</li><li style="font-size: 10pt;">Deep knowledge of digital design, RTL design, and verification flows</li><li style="font-size: 10pt;">Strong troubleshooting and analytical debugging skills with ability to debug without logs</li><li style="font-size: 10pt;"> Ability to quickly adapt to complex infrastructure environments</li><li style="font-size: 10pt;"> Excellent hands-on debug skills and attention to detail</li><li style="font-size: 10pt;">Proficient in debugging firmware and RTL code using simulation tools  </li><li style="font-size: 10pt;">Exposure to leadership or mentorship is an asset </li></ul>  ACADEMIC CREDENTIALS:  <ul type="disc"><li style="font-size: 10pt;">Bachelors or Masters degree in computer engineering/Electrical Engineering </li></ul> #LI-PM2

Collected experience requirement

8+ years