Full Chip Timing Lead

AMD · Hyderabad

Collected role description

Role overview

Full Chip Timing Lead at AMD

Owns Full chip Timing Closure

THE ROLE:

A successful person in this role would be able to work in a collaborative team environment working with other business units, central methodology team driving the group signoff and solving the critical issues with vendor.

Responsibilities

Clock build guidance using multiple methods MSCTS, Mesh
Design repeater feedback based on timing across blocks
Drive new improvement in closure
Analysis of data and feedback to PD execution team
SDC analysis and feedback
Work with PnR engineer for timing convergence
Drive the common STA methodology in the business unit
Work and collaborate with different business units, CAD and central methodology team to drive the requirement
Automation to refine and improve design signoff requirement and dashboarding
Ability to organize and present complex technical information in a crisp and concise manner.
Interact with other PPA (equivalent) teams internal to AMD
Identify best practices across AMD and industry to update and improve flow/project settings
To increase the competitiveness of each stage in AMD design flow
Ability to work with multi-level functional teams across various geographies.
Highly organized, strong affinity for automation and prioritization.
PREFERRED

Required qualifications

8+ year or more experience design signoff closure
Timing closure experience at SoC and block level
Technical depth in STA, High freq interface closure in hierarchical STA.
Multi voltage closure
Timing ECO flow
Hyperscale, Yield analysis
PnR and STA signoff correlation drive and convergence
Strong at SDC coding and debug skills
Drive new requirements and methodology to aid timing closure at SoC
Identify the gaps and support flows
Strong in scripting, Scripting language
TCL, Perl, Python, Makefile.
Drive team towards common requirements and flows
Experienced in deploying and implementing ML techniques and algorithms in physical design.
Low power physical design implementation flows ranging from RTL design through synthesis, place and route, timing closure and physical verification
Experience with different tools from various vendors - Synopsys, Cadence and Mentor.
AMD block TileBuilder and experience in lower tech nodes (5/3/2) is a plus.
ACADEMIC CREDENTIALS:
Bachelors or Masters degree in computer engineering/Electrical Engineering
#LI-SR5
Benefits offered are described: AMD benefits at a glance .
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services.
AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.
We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.
AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.
Minimum qualification: Benefits offered are described: AMD benefits at a glance . AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.

Employment details

Location: Hyderabad [India]

About the employer

At AMD, we believe technology has the power to solve the world’s most important challenges.

Benefits

From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future.

Additional role details

ADVANCE YOUR CAREER.
ADVANCE THE WORLD.
Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward.
Join us and, together, we’ll advance your career.
Full Chip Timing Lead -PD
As a member of the PD Full Chip STA closure and optimization team, you will work on SoC Full Chip Timing closure which includes high frequency CPU, HBM, DDR, Serdes interfaces.
Will be responsible for SDC validation and timing signoff execution with different team members and will work closely with the methodology and CAD teams across various geographies to achieve first pass silicon success.
THE PERSON:
Strong self-driving ability, should have excellent communication skills (both written and oral)

Collected minimum qualification

Benefits offered are described:  <a href="https://www.amd.com/en/corporate/careers/benefits.html" target="_blank" rel="noopener">AMD benefits at a glance</a>. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD’s “Responsible AI Policy” is available <a href="https://www.amd.com/en/legal/responsible-ai-use-policy.html" target="_blank" rel="noopener">here.</a> This posting is for an existing vacancy.

Collected preferred qualification

<span style="margin: 0px; padding: 0px;" data-ccp-charstyle="normaltextrun" data-ccp-charstyle-defn="{"ObjectId":"75ee5cbf-7016-4753-9550-8bbf976473cd|105","ClassId":1073872969,"Properties":[469775450,"normaltextrun",201340122,"1",134233614,"true",469778129,"normaltextrun",335572020,"1",469778324,"Default Paragraph Font"]}">Full Chip Timing Lead -PD THE ROLE: <ul><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">As a member of the PD Full Chip STA closure and optimization team, you will work on SoC Full Chip Timing closure which includes high frequency CPU, HBM, DDR, Serdes interfaces. Will be responsible for SDC validation and timing signoff execution with different team members and will work closely with the methodology and CAD teams across various geographies to achieve first pass silicon success.</li></ul> THE PERSON: <ul type="disc"><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">A successful person in this role would be able to work in a collaborative team environment working with other business units, central methodology team driving the group signoff and solving the critical issues with vendor.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Strong self-driving ability, should have excellent communication skills (both written and oral)</li></ul> KEY RESPONSIBILITIES: <ul type="disc"><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Owns Full chip Timing Closure </li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Clock build guidance using multiple methods MSCTS, Mesh </li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Design repeater feedback based on timing across blocks </li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Drive new improvement in closure </li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Analysis of data and feedback to PD execution team </li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">SDC analysis and feedback </li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Work with PnR engineer for timing convergence </li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Drive the common STA methodology in the business unit</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Work and collaborate with different business units, CAD and central methodology team to drive the requirement</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Automation to refine and improve design signoff requirement and dashboarding</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Ability to organize and present complex technical information in a crisp and concise manner.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Interact with other PPA (equivalent) teams internal to AMD</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Identify best practices across AMD and industry to update and improve flow/project settings</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">To increase the competitiveness of each stage in AMD design flow</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Ability to work with multi-level functional teams across various geographies.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Highly organized, strong affinity for automation and prioritization.</li></ul> PREFERRED EXPERIENCE: <ul type="disc"><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">8+ year or more experience design signoff closure</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Timing closure experience at SoC and block level</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Technical depth in STA, High freq interface closure in hierarchical STA.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Multi voltage closure</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Timing ECO flow</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Hyperscale, Yield analysis</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">PnR and STA signoff correlation drive and convergence</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Strong at SDC coding and debug skills</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Drive new requirements and methodology to aid timing closure at SoC</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Identify the gaps and support flows</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Strong in scripting, Scripting language experience: TCL, Perl, Python, Makefile.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Drive team towards common requirements and flows</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Experienced in deploying and implementing ML techniques and algorithms in physical design.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Low power physical design implementation flows ranging from RTL design through synthesis, place and route, timing closure and physical verification</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Experience with different tools from various vendors - Synopsys, Cadence and Mentor.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">AMD block TileBuilder and experience in lower tech nodes (5/3/2) is a plus. </li></ul> ACADEMIC CREDENTIALS: <ul type="disc"><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Bachelors or Masters degree in computer engineering/Electrical Engineering </li></ul> #LI-SR5  <span style="margin: 0px; padding: 0px; font-family: Arial, Arial_EmbeddedFont, Arial_MSFontService, sans-serif;" data-ccp-props="{"134233117":false,"134233118":false,"201341983":0,"335559738":0,"335559739":0,"335559740":240}">

Collected experience requirement

8+ years