Senior Full chip EM/IR analysis Engineer

AMD · Hyderabad

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Collected role description

Role overview

Senior Full chip EM/IR analysis Engineer at AMD

EMIR closure at Tile /Partition/Subsytem/SOC levele on a particular node

The focus of this role is to build, execute, and sign off on the Power and EMIR closure for the IP/Full chip SOC

Responsibilities

Drive Power and EMIR closure for design blocks and full-chip integration.
Align EMIR analysis phases with PD milestones .
Ensure compliance with signoff limits provided by SIPI team for given technology node
Ability to analyze EMIR violations and propose implementation choices.
Familiarity with DFx and scan architecture for EMIR considerations
Technical Leadership
Define EMIR signoff strategy, including IR drop and electromigration analysis.
Review floorplan, clocking, and bus structures for IR hotspots.
Coordinate bump allocation and power rail alignment with integration teams.
Ownership of EMIR Flow & Signoff
Collaboration & Coordination
Work closely with block owners, PD team, and integration team to execute EMIR runs.
Conduct EMIR run reviews and debug sessions with stakeholders.
Methodology & Flow Development
Maintain and improve EMIR flow
Engage with SIPI team for current profile analysis and probe pad/interposer runs.

Required qualifications

Minimum qualification: Benefits offered are described: AMD benefits at a glance . AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.

Preferred qualifications and skills

Minimum 7 to 10 years of relevant work experience.
Expertise in Synthesis , ICC2/ FC (Fusion Compiler) Physical Design flows/methodologies or equivalent tools.
Expertise in Signoff tools like Redhawk_Sc, Voltas on EMIR, PT-PX for Power signoff and Primetime for Timing
Should have worked as a go to person or technical lead for at least few full chip projects.
Strong technical leadership and ability to mentor/guide/coach design engineers to achieve and deliver project goals.
Strong inter-personal skills and ability to collaborate with teams spread across multiple geos.
Should have good scripting experience in Shell, Python, Perl, TCL, UNIX along with decode/debug old existing scripts.
Must be using AI technologies in day to day problem solving
ACADEMIC CREDENTIALS:
Bachelors or Masters degree in Electrical Engineering
#LI-SR4
Benefits offered are described: AMD benefits at a glance .
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services.
AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.
We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.
AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.

Employment details

Location: Hyderabad [India]

About the employer

At AMD, we believe technology has the power to solve the world’s most important challenges.
Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward.

Additional role details

ADVANCE YOUR CAREER.
ADVANCE THE WORLD.
From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future.
Join us and, together, we’ll advance your career.
THE ROLE:
THE PERSON:
The candidate to have a passion for complex processor architecture, digital design, and verification in general.
The candidate should be team player who has excellent communication skills and experience collaborating with other engineers located in different sites/time zones.
The candidate should have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.

Collected minimum qualification

Benefits offered are described:  <a href="https://www.amd.com/en/corporate/careers/benefits.html" target="_blank" rel="noopener">AMD benefits at a glance</a>. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD’s “Responsible AI Policy” is available <a href="https://www.amd.com/en/legal/responsible-ai-use-policy.html" target="_blank" rel="noopener">here.</a> This posting is for an existing vacancy.

Collected preferred qualification

THE ROLE: The focus of this role is to build, execute, and sign off on the Power and EMIR closure for the IP/Full chip SOC THE PERSON:  The candidate to have a passion for complex processor architecture, digital design, and verification in general. The candidate should be  team player who has excellent communication skills and experience collaborating with other engineers located in different sites/time zones. The candidate should have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.    KEY RESPONSIBILITIES:  <ul style="margin-top: 0in;"><li style="font-size: 12pt; font-family: arial, helvetica, sans-serif;">EMIR closure at Tile /Partition/Subsytem/SOC levele on a particular node</li><li style="font-size: 12pt; font-family: arial, helvetica, sans-serif;">Drive Power and EMIR closure for design blocks and full-chip integration.</li><li style="font-size: 12pt; font-family: arial, helvetica, sans-serif;">Align EMIR analysis phases with PD milestones . </li><li style="font-size: 12pt; font-family: arial, helvetica, sans-serif;">Ensure compliance with signoff limits provided by SIPI team for given technology node</li><li style="font-size: 12pt; font-family: arial, helvetica, sans-serif;">Ability to analyze EMIR violations and propose implementation choices.</li><li style="font-size: 12pt; font-family: arial, helvetica, sans-serif;">Familiarity with DFx and scan architecture for EMIR considerations</li><li style="font-size: 12pt; font-family: arial, helvetica, sans-serif;">Technical Leadership<ul style="margin-top: 0in;"><li style="list-style-type: none;"><ul style="margin-top: 0in;"><li style="font-size: 12pt; font-family: arial, helvetica, sans-serif;">Define EMIR signoff strategy, including IR drop and electromigration analysis.</li><li style="font-size: 12pt; font-family: arial, helvetica, sans-serif;">Review floorplan, clocking, and bus structures for IR hotspots.</li><li style="font-size: 12pt; font-family: arial, helvetica, sans-serif;">Coordinate bump allocation and power rail alignment with integration teams. </li></ul></li><li style="font-size: 12pt; font-family: arial, helvetica, sans-serif;">Ownership of EMIR Flow & Signoff</li><li style="font-size: 12pt; font-family: arial, helvetica, sans-serif;">Collaboration & Coordination</li></ul></li></ul><ul><li style="list-style-type: none;"><ul style="margin-top: 0in;"><li style="list-style-type: none;"><ul style="margin-top: 0in;"><li style="font-size: 12pt; font-family: arial, helvetica, sans-serif;">Work closely with block owners, PD team, and integration team to execute EMIR runs.</li><li style="font-size: 12pt; font-family: arial, helvetica, sans-serif;">Conduct EMIR run reviews and debug sessions with stakeholders.</li></ul></li><li style="font-size: 12pt; font-family: arial, helvetica, sans-serif;">Methodology & Flow Development<ul style="margin-top: 0in;"><li style="font-size: 12pt; font-family: arial, helvetica, sans-serif;">Maintain and improve EMIR flow</li><li style="font-size: 12pt; font-family: arial, helvetica, sans-serif;">Engage with SIPI team for current profile analysis and probe pad/interposer runs.</li></ul></li></ul></li></ul>  PREFERRED EXPERIENCE:   <ul><li style="list-style-type: none; font-size: 12pt; font-family: arial, helvetica, sans-serif;"><ul style="margin-top: 0in;"><li style="font-size: 12pt; font-family: arial, helvetica, sans-serif;">Minimum 7 to 10 years of relevant work experience.</li></ul></li></ul><ul style="margin-top: 0in;"><ul style="margin-top: 0in;"><li style="font-size: 12pt; font-family: arial, helvetica, sans-serif;">Expertise in Synthesis , ICC2/ FC (Fusion Compiler) Physical Design flows/methodologies or equivalent tools.</li><li style="font-size: 12pt; font-family: arial, helvetica, sans-serif;">Expertise in Signoff tools like  Redhawk_Sc, Voltas on EMIR, PT-PX for Power signoff and Primetime for Timing</li><li style="font-size: 12pt; font-family: arial, helvetica, sans-serif;">Should have worked as a go to person or technical lead for at least few full chip projects.</li><li style="font-size: 12pt; font-family: arial, helvetica, sans-serif;">Strong technical leadership and ability to mentor/guide/coach design engineers to achieve and deliver project goals.</li><li style="font-size: 12pt; font-family: arial, helvetica, sans-serif;">Strong inter-personal skills and ability to collaborate with teams spread across multiple geos.</li><li style="font-size: 12pt; font-family: arial, helvetica, sans-serif;">Should have good scripting experience in Shell, Python, Perl, TCL, UNIX along with decode/debug old existing scripts.</li><li style="font-size: 12pt; font-family: arial, helvetica, sans-serif;">Must be using AI technologies in day to day problem solving</li></ul></ul>  ACADEMIC CREDENTIALS:  <ul style="margin-top: 0in;"><li style="font-size: 12pt; font-family: arial, helvetica, sans-serif;">Bachelors or Masters degree in Electrical Engineering </li></ul> #LI-SR4

Collected experience requirement

7-10 years