RTL Design Engineer

AMD · Hyderabad

Collected role description

Role overview

RTL Design Engineer at AMD

Own the design and implementation of blocks to meet functional, timing, area and power requirements

As a member of the front-end design team, you will work closely with the architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success.

Responsibilities

Guide and review verification for these blocks
Design and implement logic functions that enable efficient test and debug
Implement automation to increase design team efficiency

Required qualifications

Minimum qualification: Benefits offered are described: AMD benefits at a glance . AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.

Preferred qualifications and skills

Strong front-end RTL engineering background
Strong communication skills, able to summarize complex problems for executives as well as drill down to details with architects and engineers
Strong analytic and problem solving skills including the ability to analyze current behavior, identify potential areas for improvement, and design of experiments
Experience with Arm architecture and APB, AXI, CHI protocols
Experience with design reuse, including RTL, constraints, and waivers
Experience with SoC level design integration
Experience with automation using scripting techniques such as PERL, Python, or Tcl
Experience with timing constraints and timing exceptions
Experience running standard quality checks such as LINT and CDC
Experience designing with multiple power domains including writing UPF
Must be a self-starter and self-motivated
ACADEMIC CREDENTIALS:
Bachelors or Masters degree in computer engineering/Electrical Engineering
#LI-PP2
Benefits offered are described: AMD benefits at a glance .
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services.
AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.
We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.
AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.

Employment details

Location: Hyderabad [India]

About the employer

WHAT YOU DO AT AMD CHANGES EVERYTHING
When you join AMD, you’ll discover the real differentiator is our culture.

Additional role details

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems.
Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary.
We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives.
Join us as we shape the future of AI and beyond. Together, we advance your career.
THE ROLE:
As a member of the Adaptive and Embedded Computing Group, you will help bring to life cutting-edge designs.
THE PERSON:
You have a passion for modern, complex processor architecture, RTL coding, and digital design in general.
You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones.
You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.

Collected minimum qualification

Benefits offered are described:  <a href="https://www.amd.com/en/corporate/careers/benefits.html" target="_blank" rel="noopener">AMD benefits at a glance</a>. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD’s “Responsible AI Policy” is available <a href="https://www.amd.com/en/legal/responsible-ai-use-policy.html" target="_blank" rel="noopener">here.</a> This posting is for an existing vacancy.

Collected preferred qualification

<span style="margin: 0px; padding: 0px; font-family: Arial, Arial_EmbeddedFont, Arial_MSFontService, sans-serif;" data-ccp-props="{"134233117":false,"134233118":false,"201341983":0,"335559738":0,"335559739":0,"335559740":240}"> THE ROLE: As a member of the Adaptive and Embedded Computing Group, you will help bring to life cutting-edge designs. As a member of the front-end design team, you will work closely with the architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success.  THE PERSON:  You have a passion for modern, complex processor architecture, RTL coding, and digital design in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.   KEY RESPONSIBILITIES:  <ul style="direction: ltr; unicode-bidi: embed; margin-top: 0in; margin-bottom: 0in;" type="disc"><li style="margin-top: 0; margin-bottom: 0; vertical-align: middle; color: black;">Own the design and implementation of blocks to meet functional, timing, area and power requirements </li><li style="margin-top: 0; margin-bottom: 0; vertical-align: middle; color: black;">Guide and review verification for these blocks</li><li style="margin-top: 0; margin-bottom: 0; vertical-align: middle; color: black;">Design and implement logic functions that enable efficient test and debug</li><li style="margin-top: 0; margin-bottom: 0; vertical-align: middle; color: black;">Implement automation to increase design team efficiency</li></ul>PREFERRED EXPERIENCE:  <ul style="direction: ltr; unicode-bidi: embed; margin-top: 0in; margin-bottom: 0in;" type="disc"><li style="margin-top: 0; margin-bottom: 0; vertical-align: middle; color: black;">Strong front-end RTL engineering background</li><li style="margin-top: 0; margin-bottom: 0; vertical-align: middle; color: black;">Strong communication skills, able to summarize complex problems for executives as well as drill down to details with architects and engineers</li><li style="margin-top: 0; margin-bottom: 0; vertical-align: middle; color: black;">Strong analytic and problem solving skills including the ability to analyze current behavior, identify potential areas for improvement, and design of experiments</li><li style="margin-top: 0; margin-bottom: 0; vertical-align: middle; color: black;">Experience with Arm architecture and APB, AXI, CHI protocols</li><li style="margin-top: 0; margin-bottom: 0; vertical-align: middle; color: black;">Experience with design reuse, including RTL, constraints, and waivers</li><li style="margin-top: 0; margin-bottom: 0; vertical-align: middle; color: black;">Experience with SoC level design integration</li><li style="margin-top: 0; margin-bottom: 0; vertical-align: middle; color: black;">Experience with automation using scripting techniques such as PERL, Python, or Tcl</li><li style="margin-top: 0; margin-bottom: 0; vertical-align: middle; color: black;">Experience with timing constraints and timing exceptions</li><li style="margin-top: 0; margin-bottom: 0; vertical-align: middle; color: black;">Experience running standard quality checks such as LINT and CDC</li><li style="margin-top: 0; margin-bottom: 0; vertical-align: middle; color: black;">Experience designing with multiple power domains including writing UPF</li><li style="margin-top: 0; margin-bottom: 0; vertical-align: middle; color: black;">Must be a self-starter and self-motivated</li></ul>  <span style="margin: 0px; padding: 0px; font-family: Arial, Arial_EmbeddedFont, Arial_MSFontService, sans-serif;" data-ccp-props="{"134233117":false,"134233118":false,"201341983":0,"335559738":0,"335559739":0,"335559740":240}"> ACADEMIC CREDENTIALS: <span style="margin: 0px; padding: 0px; font-family: Arial, Arial_EmbeddedFont, Arial_MSFontService, sans-serif;" data-ccp-props="{"134233117":false,"134233118":false,"201341983":0,"335559738":0,"335559739":0,"335559740":240}"> <ul style="margin: 0px; padding: 0px; font-family: verdana;"><li style="margin: 0px 0px 0px 24px; padding: 0px; font-size: 12pt; font-family: 'Times New Roman', 'Times New Roman_MSFontService', serif;" data-leveltext="" data-font="Symbol" data-listid="11" data-list-defn-props="{"335552541":1,"335559684":-2,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" aria-setsize="-1" data-aria-posinset="3" data-aria-level="1"><span style="margin: 0px; padding: 0px;" data-ccp-parastyle="paragraph" data-ccp-parastyle-defn="{"ObjectId":"75ee5cbf-7016-4753-9550-8bbf976473cd|104","ClassId":1073872969,"Properties":[469775450,"paragraph",201340122,"2",134233614,"true",469778129,"paragraph",335572020,"1",469777841,"Times New Roman",469777842,"Times New Roman",469777843,"Times New Roman",469777844,"Times New Roman",469769226,"Times New Roman",268442635,"24",335559740,"240",201341983,"0",134233118,"true",134233117,"true",469778324,"Normal"]}">Bachelors or Masters degree in computer engineering/Electrical Engineering<span style="margin: 0px; padding: 0px; font-family: Arial, Arial_EmbeddedFont, Arial_MSFontService, sans-serif; color: #32363a;" data-ccp-props="{"134233117":false,"134233118":false,"201341983":0,"335559738":0,"335559739":0,"335559740":240}">  <span style="margin: 0px; padding: 0px; font-family: Arial, Arial_EmbeddedFont, Arial_MSFontService, sans-serif; color: #32363a;" data-ccp-props="{"134233117":false,"134233118":false,"201341983":0,"335559738":0,"335559739":0,"335559740":240}">#LI-PP2 </li></ul>