RTL Design Manager

AMD · Hyderabad

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Collected role description

Role overview

RTL Design Manager at AMD

Responsibilities

You will also contribute to definition/evolution of IP/SOC Design methodologies and processes for future projects

Required qualifications

Engineering
Digital design and experience with RTL design in Verilog/System Verilog
Solid understanding of DFT technologies and some experience with execution of DFT flows
Experience with SOC tools including Spyglass, Questa CDC, Cadence Conformal, VCS simulation
Experience in specifying timing constraints with several clock domains and modes
Basic experience with Synopsys Design Compiler and Primetime
Experience designing with multiple power domains and islands using UPF
TCL, Python, Perl scripting
Version control systems such as Perforce, IC Manage or Git
Fluent in working with Linux and Windows environments
Leadership/Management
Strong verbal and written communication skills
Ability to organize and present complex technical information
Project planning and management of execution from Microarchitecture to Timing Closure with engineers in multiple timezones
Team building experience
Academic Credentials and Experience
Bachelors or Masters degree in Electrical Engineering with 12+ years of experience.
#LI-PP2
Benefits offered are described: AMD benefits at a glance .
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services.
AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.
We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.
AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.
Minimum qualification: Benefits offered are described: AMD benefits at a glance . AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.

Employment details

Location: Hyderabad [India]

About the employer

At AMD, we believe technology can change lives for the better.
Whether you’re designing next-gen processors, enabling AI breakthroughs, or creating go-to-market plans, every role at AMD contributes to something bigger — technology that moves the world forward.
AMD is seeking a capable and motivated SOC Design Manager to be part of Front End SOC Design Team of next generation Adaptable Compute Acceleration Platform devices

Additional role details

ADVANCE YOUR CAREER.
ADVANCE THE WORLD.
It can heal us, entertain us, and make us more connected, productive, and understanding of the world around us.
And we’re looking for talent who feel the same: people who want to leave the planet better than they found it, those who don’t shy away from humanity’s challenges but are determined to help solve them.
AMD is powering the next generation of supercomputing, high-performance computing, cloud, and AI.
THE ROLE:
You will manage team working on design and implementation of high-performance, low-power SOCs and SOC Chiplets targeting a wide range of applications as well as customer specific products
This high visibility and critical role will require technical leadership in developing microarchitecture, implementing functions in RTL, integrating IP from internal and external sources, ensuring quality and getting design ready for synthesis.
THE PERSON:
Successful candidate will have an SOC/ASIC Design background, team/project management experience, would have participated in several silicon design projects with increasing level of scope/responsibilities and has a history of achieving results through effective execution
KEY RESPONISIBILITES:
Team management (hiring, coaching, reviewing and retaining engineers)
Project Planning
Tracking Project Execution and reporting of key metrics
Managing Design reviews around feature and quality
Retrospectives and project wind-down
Crossfunctional stakeholder management (marketing, architecture, verification, physical design, chip integration, applications, methodology experts, management)
Participate in tapeout checklists and reviews
Improve processes for team through AI adoption and traditional automation

Collected minimum qualification

Benefits offered are described:  <a href="https://www.amd.com/en/corporate/careers/benefits.html" target="_blank" rel="noopener">AMD benefits at a glance</a>. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD’s “Responsible AI Policy” is available <a href="https://www.amd.com/en/legal/responsible-ai-use-policy.html" target="_blank" rel="noopener">here.</a> This posting is for an existing vacancy.

Collected preferred qualification

THE ROLE:<ul style="margin-top: 0in;"><li>AMD is seeking a capable and motivated SOC Design Manager to be part of Front End SOC Design Team of next generation Adaptable Compute Acceleration Platform devices</li><li>You will manage team working on design and implementation of high-performance, low-power SOCs and SOC Chiplets targeting a wide range of applications as well as customer specific products</li><li>This high visibility and critical role will require technical leadership in developing microarchitecture, implementing functions in RTL, integrating IP from internal and external sources, ensuring quality and getting design ready for synthesis.</li><li>You will also contribute to definition/evolution of IP/SOC Design methodologies and processes for future projects</li></ul>THE PERSON:<ul style="margin-top: 0in;"><li>Successful candidate will have an SOC/ASIC Design background, team/project management experience, would have participated in several silicon design projects with increasing level of scope/responsibilities and has a history of achieving results through effective execution</li></ul>KEY RESPONISIBILITES:<ul style="margin-top: 0in;"><li>Team management (hiring, coaching, reviewing and retaining engineers)</li><li>Project Planning</li><li>Tracking Project Execution and reporting of key metrics</li><li>Managing Design reviews around feature and quality</li><li>Retrospectives and project wind-down</li><li>Crossfunctional stakeholder management (marketing, architecture, verification, physical design, chip integration, applications, methodology experts, management)</li><li>Participate in tapeout checklists and reviews</li><li>Improve processes for team through AI adoption and traditional automation</li></ul>REQUIRED EXPERIENCE:<ul style="margin-top: 0in;"><li>Engineering<ul style="margin-top: 0in;"><li>Digital design and experience with RTL design in Verilog/System Verilog</li><li>Solid understanding of DFT technologies and some experience with execution of DFT flows</li><li>Experience with SOC tools including Spyglass, Questa CDC, Cadence Conformal, VCS simulation</li><li>Experience in specifying timing constraints with several clock domains and modes</li><li>Basic experience with Synopsys Design Compiler and Primetime</li><li>Experience designing with multiple power domains and islands using UPF</li><li>TCL, Python, Perl scripting</li><li>Version control systems such as Perforce, IC Manage or Git</li><li>Fluent in working with Linux and Windows environments</li></ul></li></ul><ul style="margin-top: 0in;"><li>Leadership/Management<ul style="margin-top: 0in;"><li>Strong verbal and written communication skills</li><li>Ability to organize and present complex technical information</li><li>Project planning and management of execution from Microarchitecture to Timing Closure with engineers in multiple timezones</li><li>Team building experience</li></ul></li></ul>Academic Credentials and Experience<ul style="margin-top: 0in;"><li><span style="margin: 0px; padding: 0px;" data-ccp-parastyle="paragraph" data-ccp-parastyle-defn="{"ObjectId":"acd06137-8b58-41e2-a034-fbb48e07259f|122","ClassId":1073872969,"Properties":[469775450,"paragraph",201340122,"2",134233614,"true",469778129,"paragraph",335572020,"1",469777841,"Times New Roman",469777842,"Times New Roman",469777843,"Times New Roman",469777844,"Times New Roman",469769226,"Times New Roman",134233118,"true",134233117,"true",469778324,"Normal"]}">Bachelors or Masters degree in Electrical Engineering with 12+ years of experience.</li></ul> #LI-PP2

Collected experience requirement

12+ years