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RTL IP Design Engineer

AMD · Hyderabad

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Collected role description

Role overview

RTL IP Design Engineer at AMD

Define product features and micro-architecture requirements.

As a member of the front-end design/integration team, you will work closely with the architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success.

Responsibilities

  • Create technical specifications for IP blocks to meet those requirements, and provide technical guidance to design teams
  • Work cross functionally with IP/Domain architects to identify and assess complex technical issues/risks and develop solutions to achieve product requirements
  • Work on high quality design deliverables with design qualifications like lint, CDC, synthesis and hand-off documentation
  • Knowledge sharing and other contributions to Platform & System Architecture
  • Work closely with Design teams for Area and Floorplan refinement, Verification Test plan reviews, Timing targets and sign offs
  • Support Post-Si teams for Product Performance, Power and functional issues debug/resolution

Required qualifications

  • Minimum qualification: Benefits offered are described: AMD benefits at a glance . AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.

Preferred qualifications and skills

  • A minimum of 10 years of experience is required
  • Proven experience in Silicon IP development process and design methodologies
  • Experience with Verilog RTL design, simulation, linting, CDC and other design qualifications, scripting etc..
  • Detailed understanding and proven track record of developing leading edge networking IP solutions such as Ethernet and industry standard security protocols
  • Detailed knowledge of PCIe is a plus
  • Excellent communication and presentation skills
  • Adept at collaboration among top-thinkers and senior architects with strong interpersonal skills to work across teams in different geographies
  • ACADEMIC CREDENTIALS:
  • Bachelors or Masters degree in computer engineering/Electrical Engineering
  • #LI-SK3
  • Benefits offered are described: AMD benefits at a glance .
  • AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services.
  • AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.
  • We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
  • AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.
  • AMD’s “Responsible AI Policy” is available here.
  • This posting is for an existing vacancy.

Employment details

  • Location: Hyderabad [India]

About the employer

  • WHAT YOU DO AT AMD CHANGES EVERYTHING
  • When you join AMD, you’ll discover the real differentiator is our culture.

Additional role details

  • At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems.
  • Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary.
  • We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives.
  • Join us as we shape the future of AI and beyond. Together, we advance your career.
  • RTL IP Design Engineer
  • THE ROLE:
  • As a member of the Networking Technology Solutions Group, you will help bring to life cutting-edge designs.
  • This exciting position as MTS will provide the opportunity to demonstrate strong technical collaboration across the design hierarchy from architecture to productization.
  • Join us in providing innovative IP solutions as we embark on our journey into delivering the leading-edge IP Solutions for data center networking solutions
  • THE PERSON:
  • You have excellent communication and presentation skills, demonstrated through technical publications, presentations, trainings, executive briefings, etc.
  • You are highly adept at collaboration among top-thinkers and engineers alike, ready to mentor and guide, and help to elevate the knowledge and skills of the team around you.

Collected minimum qualification

<p style="margin: 0px;"><span style="font-size: 12pt;"><em><span style="font-family: 'Arial',sans-serif; color: black;">Benefits offered are described:&nbsp; </span></em><span style="font-family: 'Arial',sans-serif; color: black;"><a href="https://www.amd.com/en/corporate/careers/benefits.html" target="_blank" rel="noopener">AMD benefits at a glance</a>.</span></span></p><p style="margin: 0px;"><span style="color: black; font-size: 12pt;">&nbsp;</span></p><p style="margin: 0px;"><span style="font-size: 12pt;"><em><span style="font-family: 'Arial',sans-serif; color: black;">AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.&nbsp;&nbsp; We encourage applications from all qualified candidates and will accommodate applicants&rsquo; needs under the respective laws throughout all stages of the recruitment and selection process.</span></em></span></p><p style="margin: 0px;"><span style="color: black; font-size: 12pt;">&nbsp;</span></p><p style="margin: 0px;"><span style="font-size: 12pt;"><em><span style="font-family: 'Arial',sans-serif; color: black;">AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.&nbsp; AMD&rsquo;s &ldquo;Responsible AI Policy&rdquo; is available <a href="https://www.amd.com/en/legal/responsible-ai-use-policy.html" target="_blank" rel="noopener">here.</a></span></em></span></p><p style="margin: 0px;"><span style="font-size: 12pt;"><em><span style="font-family: 'Arial',sans-serif; color: black;">&nbsp;</span></em></span></p><p style="margin: 0px;"><span style="font-size: 12pt;"><em><span style="font-family: 'Arial',sans-serif; color: black;">This posting is for an existing vacancy.</span></em></span></p>

Collected preferred qualification

<p style="margin: 0px; padding: 0px; color: windowtext;"><span style="font-size: 12pt;"><span style="margin: 0px; padding: 0px; font-family: Arial, Arial_EmbeddedFont, Arial_MSFontService, sans-serif;" data-ccp-props="{&quot;134233117&quot;:false,&quot;134233118&quot;:false,&quot;201341983&quot;:0,&quot;335551550&quot;:2,&quot;335551620&quot;:2,&quot;335559738&quot;:0,&quot;335559739&quot;:0,&quot;335559740&quot;:240}"><strong>RTL IP Design Engineer</strong>&nbsp;</span></span></p><p style="margin: 0px; padding: 0px; color: windowtext;"><span style="font-size: 12pt;"><span style="margin: 0px; padding: 0px; font-family: Arial, Arial_EmbeddedFont, Arial_MSFontService, sans-serif;" data-contrast="auto"><span style="margin: 0px; padding: 0px;" data-ccp-charstyle="eop"> </span></span><span style="margin: 0px; padding: 0px; font-family: Arial, Arial_EmbeddedFont, Arial_MSFontService, sans-serif;" data-ccp-props="{&quot;134233117&quot;:false,&quot;134233118&quot;:false,&quot;201341983&quot;:0,&quot;335559738&quot;:0,&quot;335559739&quot;:0,&quot;335559740&quot;:240}">&nbsp;</span></span></p><p style="margin: 0px;"><strong><span style="font-size: 12.0pt; font-family: 'Arial',sans-serif; color: #32363a;">THE ROLE:</span></strong>&nbsp;</p><p style="margin: 0px;"><span style="font-size: 12.0pt; font-family: 'Arial',sans-serif; color: #32363a;">As a member of the Networking Technology Solutions Group, you will help bring to life cutting-edge designs. As a member of the front-end design/integration team, you will work closely with the architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success.<br><br></span></p><p style="margin: 0px;"><span style="font-size: 12.0pt; font-family: 'Arial',sans-serif; color: #32363a;">This exciting position as MTS will provide the opportunity to demonstrate strong technical collaboration across the design hierarchy from architecture to productization. Join us in providing innovative IP solutions as we embark on our journey into delivering the leading-edge IP Solutions for data center networking solutions</span></p><p style="margin: 0px;">&nbsp;</p><p style="margin: 0px;"><strong><span style="font-size: 12.0pt; font-family: 'Arial',sans-serif; color: #32363a;">THE PERSON:</span></strong></p><p style="margin: 0px;"><span style="font-size: 12.0pt; font-family: 'Arial',sans-serif; color: #32363a;">You have excellent communication and presentation skills, demonstrated through technical publications, presentations, trainings, executive briefings, etc.&nbsp; You are highly adept at collaboration among top-thinkers and engineers alike, ready to mentor and guide, and help to elevate the knowledge and skills of the team around you.</span></p><p style="margin: 0px;">&nbsp;</p><p style="margin: 0px;"><strong><span style="font-size: 12.0pt; font-family: 'Arial',sans-serif; color: #32363a;">KEY RESPONSIBILITIES:&nbsp;</span></strong></p><ul style="margin-top: 0in;"><li style="color: #32363a; margin-bottom: 0in;"><span style="font-size: 12.0pt; font-family: 'Arial',sans-serif;">Define product features and micro-architecture requirements. Create technical specifications for IP blocks to meet those requirements, and provide technical guidance to design teams&nbsp;</span></li><li style="color: #32363a; margin-bottom: 0in;"><span style="font-size: 12.0pt; font-family: 'Arial',sans-serif;">Work cross functionally with IP/Domain architects to identify and assess complex technical issues/risks and develop solutions to achieve product requirements&nbsp;</span></li></ul><ul style="margin-top: 0in;"><li style="color: #32363a; margin-bottom: 0in;"><span style="font-size: 12.0pt; font-family: 'Arial',sans-serif;">Work on high quality design deliverables with design qualifications like lint, CDC, synthesis and hand-off documentation </span></li><li style="color: #32363a; margin-bottom: 0in;"><span style="font-size: 12.0pt; font-family: 'Arial',sans-serif;">Knowledge sharing and other contributions to Platform &amp; System Architecture&nbsp;&nbsp;</span></li><li style="color: #32363a; margin-bottom: 0in;"><span style="font-size: 12.0pt; font-family: 'Arial',sans-serif;">Work closely with Design teams for Area and Floorplan refinement, Verification Test plan reviews, Timing targets and sign offs&nbsp;</span></li></ul><ul style="margin-top: 0in;"><li style="color: #32363a; margin-bottom: 0in;"><span style="font-size: 12.0pt; font-family: 'Arial',sans-serif;">Support Post-Si teams for Product Performance, Power and functional issues debug/resolution&nbsp;</span></li></ul><p style="margin-bottom: 0in;"><strong><span style="font-size: 12.0pt; font-family: 'Arial',sans-serif; color: #32363a;">&nbsp;</span></strong></p><p style="margin-bottom: 0in;"><strong><span style="font-size: 12.0pt; font-family: 'Arial',sans-serif; color: #32363a;">PREFERRED EXPERIENCE:</span></strong></p><ul><li><span style="font-size: 12.0pt; font-family: 'Arial',sans-serif; color: black;">A minimum of 10 years of experience is required</span></li><li><span style="font-size: 12.0pt; font-family: 'Arial',sans-serif; color: #32363a;">Proven experience in Silicon IP development process and design methodologies</span></li><li><span style="font-size: 12.0pt; font-family: 'Arial',sans-serif; color: #32363a;">Experience with Verilog RTL design, simulation, linting, CDC and other design qualifications, scripting etc..</span></li><li><span style="font-size: 12.0pt; font-family: 'Arial',sans-serif;">Detailed understanding and proven track record of developing leading edge networking IP solutions such as Ethernet and industry standard security protocols</span></li><li><span style="font-size: 12.0pt; font-family: 'Arial',sans-serif;">Detailed knowledge of PCIe is a plus</span></li><li style="color: #32363a;"><span style="font-size: 12.0pt; font-family: 'Arial',sans-serif;">Excellent communication and presentation skills </span></li><li style="color: #32363a;"><span style="font-size: 12.0pt; font-family: 'Arial',sans-serif;">Adept at collaboration among top-thinkers and senior architects with strong interpersonal skills to work across teams in different geographies&nbsp;</span></li></ul><p style="margin-bottom: 0in;"><span style="font-size: 12.0pt; font-family: 'Times New Roman',serif;">&nbsp;</span></p><p style="margin-bottom: 0in;"><strong><span style="font-size: 12.0pt; font-family: 'Arial',sans-serif; color: black;">ACADEMIC CREDENTIALS:</span></strong></p><p style="margin-left: .5in;"><span style="font-size: 12.0pt; font-family: 'Arial',sans-serif; color: black;">&nbsp;</span></p><ul style="margin-top: 0in;"><li style="color: black;"><span style="font-size: 12.0pt; font-family: 'Arial',sans-serif;">Bachelors or Masters degree in computer engineering/Electrical Engineering&nbsp;</span></li></ul><p><span style="font-size: 12.0pt; font-family: 'Arial',sans-serif;">&nbsp; &nbsp; &nbsp;&nbsp;<br>#LI-SK3<br></span></p><p style="margin: 0px;">&nbsp;</p><p style="margin: 0px;">&nbsp;</p>

Collected experience requirement

10+ years