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Principal Engineer Digital Design

Infineon · Bangalore

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Collected role description

Role overview

Principal Engineer Digital Design at Infineon

Own end-to-end IP definition from requirements through architecture, implementation, verification, and handoff.

This role drives architecture closure across algorithm intent, fixed-point implementation, RTL micro-architecture, register/bus interfaces, verification strategy, and implementation readiness.

Responsibilities

  • in your new role
  • Technical Ownership
  • Translate system and product requirements into a clear IP micro-architecture and execution plan.
  • Drive closure on algorithm intent, control behavior, filter architecture, latency budgets, and implementation trade-offs.
  • Review and converge control/filter algorithm definition, sampling intent, and expected behavior with signal-processing architects.
  • Drive fixed-point architecture decisions including numeric precision, dynamic range, saturation, rounding, scaling, and pipeline placement.
  • Oversee RTL architecture for filter data path, coefficient programming, update paths, loop delays, state machines, and control logic.
  • Own top-level design decisions affecting timing, CDC, reset strategy, area, power, and implementation robustness.
  • Guide register architecture, status/control visibility, firmware programmability, and system integration behavior.
  • Drive architecture and RTL for AHB/PM Bus/AVS or other system-facing interfaces, including arbitration and error handling.
  • Define verification goals and signoff expectations jointly with DV and AMS verification leads.
  • Ensure availability of golden models, bit-true checking strategy, coverage goals, and end-to-end latency checks.
  • Drive closure on corner cases including overflow, convergence, saturation recovery, limit cycles, reset behavior, and protocol exceptions.
  • Ensure analog assumptions, abstraction boundaries, and mixed-signal interaction points are verified appropriately.
  • Review and close functional gaps across RTL, DV, DMS/AMS, and system validation.
  • Break down execution into work packages, milestones, dependencies, and risk mitigation plans.
  • Your Profile

Required qualifications

  • and skills to help you succeed
  • Bachelor’s or Master’s degree in Electrical Engineering,
  • Strong experience leading digital or mixed-signal-adjacent IP development.
  • Strong understanding of control loops, DSP/filter implementations, or fixed-point digital signal processing.
  • Contact:
  • VidhiAshok.Thakkar@infineon.com
  • #WeAreIn for driving decarbonization and digitalization.
  • As a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT.
  • Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals.
  • Be a part of making life easier, safer and greener.
  • Are you in?
  • We are on a journey to create the best Infineon for everyone.
  • This means we embrace diversity and inclusion and welcome everyone for who they are.
  • At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities.
  • We base our recruiting decisions on the applicant´s experience and skills. Learn more about our various contact channels.
  • Please let your recruiter know if they need to pay special attention to something in order to enable your participation in the interview process.
  • Click here for more information about Diversity & Inclusion at Infineon.

Employment details

  • Location: Bangalore BTP

Additional role details

  • The Multi Phase controller IP Lead is responsible for end-to-end definition, execution, and delivery of a control- and filter-centric signal processing digital IP that interfaces with high complexity AFEs.
  • The IP Lead aligns System modelling, Analog, RTL, DV, and DMS/AMS teams to ensure the IP meets functional, performance, latency, quality, and integration goals.
  • Your Role