Senior Engineer RTL Design

<h1><b>Position:</b></h1>Senior Engineer RTL Design<p style="text-align:inherit"></p><p style="text-align:inherit"></p><h1><b>Job Description:</b></h1><p>Principal Accountabilities<br /> RTL development for ASIC / FPGA<br /> Responsible for completion of front end design flow (spec to RTL / Netlist) <br /> Design, micro architect &amp; do RTL coding, Lint, CDC<br /> Support existing sustenance designs <br />* Collaborate with Hardware board design engineers for system level designs, Board level block diagram design and validation of hardware, utilizing the Company specified hardware design tools</p><p><br />Job Complexity<br />● Requires in-depth knowledge and experience<br />● Solves complex problems; takes a new perspective using existing solutions<br />● Works independently; receives minimal guidance<br />● Acts as a resource for colleagues with less experience<br />● Represents the level at which career may stabilize for many years or even until retirement<br />● Contributes to process improvements<br />● Typically resolves problems using existing solutions<br />● Provides informal guidance to junior staff<br />● Works with minimal guidance</p><p>Experience / Education<br />Typically requires 5–7 years of related experience with a 4 year degree; or 3 years and an advanced degree; or equivalent work experience.</p><p style="text-align:inherit"></p><p style="text-align:inherit"></p><h1><b>Location:</b></h1>IN-GJ-Ahmedabad, India-Aryan Bld-2 (eInfochips)<p style="text-align:inherit"></p><p style="text-align:inherit"></p><h1><b>Time Type:</b></h1>Full time<h1></h1><p style="text-align:inherit"></p><h1><b>Job Category:</b></h1>Engineering Services