Principal Design Engineer

Role overview

Principal Design Engineer at Cadence

Responsibilities

• Help us solve what others can’t.

Required qualifications

• Strong hands-on UVM and System Verilog coding experience and functional verification environment development is required.

Employment details

• Location: BANGALORE, NOIDA

About the employer

• At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Additional role details

• BE/BTech/ME/MTech - Electrical / Electronics / VLSI with an experience as a design and verification engineer.
• 8+ years of Design Verification experience with SV/UVM
• Strong background on functional verification fundamentals, environment planning, test plan generation, environment development is a must.
• Design Verification experience verifying complex designs and leading projects from concept to verification closure.
• Prior experience in IP verification of memory IP (DDR/HBM/GDDR) would be an added advantage.
• We’re doing work that matters.