Senior Lead Engineer - STA

Role overview

Senior Lead Engineer - STA at NXP Semiconductors

Required qualifications

• leading capabilities on signoff function.
• worked on SDF generation and validation.
• all knowledge of SI closure.
• exposure to higher tech nodes such as 16nm and 5nm.
• Must be conversant with physical design flows and functions and must possess good knowledge of placement, CTS and Routing.
• The individual contributes to problem solving related to physical design.
• Contributes to define best Physical design strategy per technology node.
• More information about NXP in India...
• #LI-2734

Employment details

• Location: Noida [India]

Additional role details

• The Digital Physical Design Engineer is responsible for complete STA signoff for the SOC or Subsystem.
• The individual is responsible for writing timing constraints, interacting with the counterpart functions, such as Frontend, DFT and IP to write correct constraints, refining constraints throughout SOC design cycle and constraints validation.
• The individual must have exposure of AI and use AI in STA activities.
• The individual is responsible for complete timing signoff till the tapeout for subsystem or full chip.