CPU Verification Engineer

<strong class="jdheading"></strong><br><br><p style="margin: 0px;"><span style="font-size: 12pt; font-family: arial, helvetica, sans-serif;"><strong>ADVANCE YOUR CAREER. ADVANCE THE WORLD. </strong></span></p><p style="margin: 0px;"><span style="font-size: 12pt; font-family: arial, helvetica, sans-serif;">At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. </span></p><p style="margin: 0px;"> </p><p style="margin: 0px;"><span style="font-size: 12pt; font-family: arial, helvetica, sans-serif;">Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career.</span></p> <br><strong class="jdheading"></strong><br><br><p style="margin: 0px; padding: 0px; color: windowtext;"> </p><p style="margin: 0px; padding: 0px; color: windowtext;"><span style="margin: 0px; padding: 0px; font-size: 12pt; font-family: Arial, Arial_EmbeddedFont, Arial_MSFontService, sans-serif; color: #32363a;" data-ccp-props="{"201341983":0,"335551550":2,"335551620":2,"335559739":0,"335559740":240}"> </span></p><p style="margin: 0in; margin-left: .375in; font-family: Arial; font-size: 12.0pt; color: #32363a;"><span style="font-weight: bold;">THE ROLE:</span> </p><p style="margin: 0in; margin-left: .375in; font-family: Arial; font-size: 12.0pt; color: #32363a;">The Core design and verification team is responsible for development of ‘High performance and Ultralow power x86 microprocessor core’. The role provides a unique opportunity to work at the micro-architectural level of the next-gen Core, with exposure to designs that defines the next wave of client (laptops/ultra-books/think-clients) and custom designs. The multi-billion gate complexity and high-frequency (GHz) design development gives the learning experience of the latest and greatest design and verification methodologies, using cutting edge advanced technology nodes.</p><p style="margin: 0in; margin-left: .375in; font-family: Calibri; font-size: 11.0pt;"> </p><p style="margin: 0in; margin-left: .375in; font-family: Arial; font-size: 12.0pt;"><span style="font-weight: bold;">THE PERSON:</span></p><p style="margin: 0in; margin-left: .375in; font-family: Arial; font-size: 12.0pt;">Candidates should have solid track record of working on complex designs with hands on experience on architecting and developing test-bench, test-bench components, test-planning and execution of testplan, coverage development and closure. Candidate should have working experience with global teams spread across different geography and time-zones.</p><p style="margin: 0in; margin-left: .375in; font-family: Calibri; font-size: 11.0pt;"> </p><p style="margin: 0in; margin-left: .375in; font-family: Arial; font-size: 12.0pt; color: #32363a;"><span style="font-weight: bold;">KEY RESPONSIBLITIES:</span></p><ul style="direction: ltr; unicode-bidi: embed; margin-top: 0in; margin-bottom: 0in;" type="disc"><li style="margin-top: 0; margin-bottom: 0; vertical-align: middle; color: black;"><span style="font-family: arial; font-size: 12.0pt;">Verification of Power management features of complex CPU Designs</span></li><li style="margin-top: 0; margin-bottom: 0; vertical-align: middle; color: black;"><span style="font-family: arial; font-size: 12.0pt;">Architecting and development of testbench, test-bench components for complex system management/contol features including clock, reset and power management functionality of CPU cores</span></li><li style="margin-top: 0; margin-bottom: 0; vertical-align: middle; color: black;"><span style="font-family: arial; font-size: 12.0pt;">Development of detailed test plans and driving the execution of test plan, including functional coverage.</span></li><li style="margin-top: 0; margin-bottom: 0; vertical-align: middle; color: black;"><span style="font-family: arial; font-size: 12.0pt;">Understanding the existing test bench setup and look for opportunities to improve the existing test bench.</span></li><li style="margin-top: 0; margin-bottom: 0; vertical-align: middle; color: black;"><span style="font-family: arial; font-size: 12.0pt;">Adhering to coding guideline practices, develop and implement code review process.</span></li><li style="margin-top: 0; margin-bottom: 0; vertical-align: middle; color: black;"><span style="font-family: arial; font-size: 12.0pt;">Collaborate with global design verification teams and drive effectively the execution of the verification plans.</span></li><li style="margin-top: 0; margin-bottom: 0; vertical-align: middle; color: black;"><span style="font-family: arial; font-size: 12.0pt;">Your commitment to innovating as a team demonstrated through excellent communication, knowledge of proper documentation techniques, and independently driving tasks to completion.</span></li></ul><p style="margin: 0in; margin-left: .375in; font-family: Arial; font-size: 12.0pt; color: #32363a;"><span style="font-weight: bold;">PREFERRED EXPERIENCE:</span></p><ul style="direction: ltr; unicode-bidi: embed; margin-top: 0in; margin-bottom: 0in;" type="disc"><li style="margin-top: 0; margin-bottom: 0; vertical-align: middle; color: black;"><span style="font-family: arial; font-size: 12.0pt;">ASIC design verification experience 2 to 5 years.</span></li><li style="margin-top: 0; margin-bottom: 0; vertical-align: middle; color: black;"><span style="font-family: arial; font-size: 12.0pt;">Strong understanding the design and verification life cycle.</span></li><li style="margin-top: 0; margin-bottom: 0; vertical-align: middle; color: black;"><span style="font-family: arial; font-size: 12.0pt;">Hands on verification experience with C/C++/SystemVerilog testbench development.</span></li><li style="margin-top: 0; margin-bottom: 0; vertical-align: middle; color: black;"><span style="font-family: arial; font-size: 12.0pt;">Hands on experience with coverage planning, coding and coverage closure.</span></li><li style="margin-top: 0; margin-bottom: 0; vertical-align: middle; color: black;"><span style="font-family: arial; font-size: 12.0pt;">Experience with x86, ARM or any other industry standard microprocessor architecture and ACPI standards.</span></li><li style="margin-top: 0; margin-bottom: 0; vertical-align: middle; color: black;"><span style="font-family: arial; font-size: 12.0pt;">Experience in clocking, reset, power-up sequences and power management verification.</span></li><li style="margin-top: 0; margin-bottom: 0; vertical-align: middle; color: black;"><span style="font-family: arial; font-size: 12.0pt;">Understanding of low power design verification techniques is a plus.</span></li><li style="margin-top: 0; margin-bottom: 0; vertical-align: middle; color: black;"><span style="font-family: arial; font-size: 12.0pt;">exposure to GLS, power aware verification and post-si verification is a plus</span></li></ul><p style="margin: 0in; margin-left: .375in; font-family: arial; font-size: 12.0pt; color: black;"> </p><p style="margin: 0in; margin-left: .375in; font-family: Calibri; font-size: 11.0pt;"> </p><p style="margin: 0in; margin-left: .375in; font-family: Arial; font-size: 12.0pt; color: black;"><span style="font-weight: bold;">ACADEMIC CREDENTIALS:</span></p><ul style="direction: ltr; unicode-bidi: embed; margin-top: 0in; margin-bottom: 0in;" type="disc"><li style="margin-top: 0; margin-bottom: 0; vertical-align: middle; color: #32363a;"><span style="font-family: Arial; font-size: 12.0pt;">Bachelors or Masters degree in computer engineering/Electrical Engineering </span></li><li style="margin-top: 0; margin-bottom: 0; vertical-align: middle; color: #32363a;"><span style="font-family: Arial; font-size: 12.0pt;">#LI-BM2 </span></li></ul> <br><strong class="jdheading"></strong><br><br><p style="margin: 0px;"><span style="font-size: 12pt;"><em><span style="font-family: 'Arial',sans-serif; color: black;">Benefits offered are described: </span></em><span style="font-family: 'Arial',sans-serif; color: black;"><a href="https://www.amd.com/en/corporate/careers/benefits.html" target="_blank" rel="noopener">AMD benefits at a glance</a>.</span></span></p><p style="margin: 0px;"><span style="color: black; font-size: 12pt;"> </span></p><p style="margin: 0px;"><span style="font-size: 12pt;"><em><span style="font-family: 'Arial',sans-serif; color: black;">AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.</span></em></span></p><p style="margin: 0px;"><span style="color: black; font-size: 12pt;"> </span></p><p style="margin: 0px;"><span style="font-size: 12pt;"><em><span style="font-family: 'Arial',sans-serif; color: black;">AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available <a href="https://www.amd.com/en/legal/responsible-ai-use-policy.html" target="_blank" rel="noopener">here.</a></span></em></span></p><p style="margin: 0px;"><span style="font-size: 12pt;"><em><span style="font-family: 'Arial',sans-serif; color: black;"> </span></em></span></p><p style="margin: 0px;"><span style="font-size: 12pt;"><em><span style="font-family: 'Arial',sans-serif; color: black;">This posting is for an existing vacancy.</span></em></span></p>