Senior Analog layout Engineer

AMD · Hyderabad

Collected role description

ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career. THE ROLE: AMD is looking for a talented individual to join the Design Engineering team as a Staff Analog Layout Design Engineer in advanced process technology node 7nm and below. design high performance analog and digital circuits such as ADCs, DACs, PLLs, HBM, GDDR, DDR, LPDDR, References, Custom IOs, LDO, ESD which are integrated into AMD products THE PERSON: An experienced Analog Layout design engineer should be innovative, collaborative, meticulous, and curious. KEY RESPONSIBILITIES: <ul><li>Strong foundation in layout design for mixed analog / digital ICs with 7nm and below CMOS process geometries experience</li><li>Experience in the layout of high performance data converters and / or high speed (GHz) circuit design would be an advantage</li><li>Extensive Floorplanning, power grid and signal flow planning experience</li><li>Experience in LVS, DRC, ERC, ANT, ESD, Latch-up, EMIR and Reliability</li><li>Excellent understanding of signal and clock shielding and isolation techniques</li><li>Excellent understanding of process non-idealities such as STI stress, well proximity effect and CMP effects and design strategies to mitigate these effects</li><li>Excellent written and oral communication skills are also required</li><li>Ability to work well as part of a team</li><li>Excellent problem solving skills</li><li>Strong foundation in layout design for mixed analog / digital ICs with 7nm and below CMOS process geometries experience</li><li>Experience in the layout of high performance data converters and / or high speed (GHz) circuit design would be an advantage</li><li>Extensive Floorplanning, power grid and signal flow planning experience</li><li>Experience in LVS, DRC, ERC, ANT, ESD, Latch-up, EMIR and Reliability</li><li>Excellent understanding of signal and clock shielding and isolation techniques</li><li>Excellent understanding of process non-idealities such as STI stress, well proximity effect and CMP effects and design strategies to mitigate these effects</li><li>Excellent written and oral communication skills are also required</li><li>Ability to work well as part of a team</li><li>Excellent problem solving skills</li></ul>PREFERRED EXPERIENCE: <ul><li>Must have detailed knowledge of CMOS circuit theory.</li><li>Must have ability to communicate with various teams to articulate specs and requirements as they pertain to layout</li><li>Layout design and verification experience using Cadence Virtuoso and Mentor Calibre tools</li><li>Must have at least 8 years of relevant or comparable experience doing analog layout design</li><li>Knowledge of chip level integration and ESD concepts a plus</li><li>Experience in LVS, DRC, ERC, ANT, ESD, Latch-up, EMIR and Reliability</li><li>Good understanding of signal and clock shielding and isolation techniques</li><li>Ability to work well as part of a team</li></ul>ACADEMIC CREDENTIALS: <ul style="margin: 0px; padding: 0px; font-family: verdana;"><li style="margin: 0px 0px 0px 24px; padding: 0px; font-size: 12pt; font-family: Arial, Arial_MSFontService, sans-serif;" data-leveltext="" data-font="Symbol" data-listid="12" data-list-defn-props="{"335552541":1,"335559684":-2,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" aria-setsize="-1" data-aria-posinset="2" data-aria-level="1">Bachelors or Masters degree in Electronics and Communication Engineering with 4+Yrs of exp</li></ul><p style="margin-top: 0px;margin-right: 0px;margin-bottom: 0px;margin-left: 24px;padding-top: 0px;padding-right: 0px;padding-bottom: 0px;padding-left: 0px;font-size: 12pt;font-family: Arial, Arial_MSFontService, sans-serif;"> <p style="margin-top: 0px;margin-right: 0px;margin-bottom: 0px;margin-left: 24px;padding-top: 0px;padding-right: 0px;padding-bottom: 0px;padding-left: 0px;font-size: 12pt;font-family: Arial, Arial_MSFontService, sans-serif;">#LI-SR4 Benefits offered are described: <a href="https://www.amd.com/en/corporate/careers/benefits.html" target="_blank" rel="noopener">AMD benefits at a glance</a>. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available <a href="https://www.amd.com/en/legal/responsible-ai-use-policy.html" target="_blank" rel="noopener">here.</a> This posting is for an existing vacancy.

Collected minimum qualification

Benefits offered are described:  <a href="https://www.amd.com/en/corporate/careers/benefits.html" target="_blank" rel="noopener">AMD benefits at a glance</a>. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD’s “Responsible AI Policy” is available <a href="https://www.amd.com/en/legal/responsible-ai-use-policy.html" target="_blank" rel="noopener">here.</a> This posting is for an existing vacancy.

Collected preferred qualification

THE ROLE: AMD is looking for a talented individual to join the Design Engineering team as a Staff Analog Layout Design Engineer in advanced process technology node 7nm and below. design high performance analog and digital circuits such as ADCs, DACs, PLLs, HBM, GDDR, DDR, LPDDR, References, Custom IOs, LDO, ESD which are integrated into AMD products  THE PERSON: An experienced Analog Layout design engineer should be innovative, collaborative, meticulous, and curious. KEY RESPONSIBILITIES: <ul><li>Strong foundation in layout design for mixed analog / digital ICs with 7nm and below CMOS process geometries experience</li><li>Experience in the layout of high performance data converters and / or high speed (GHz) circuit design would be an advantage</li><li>Extensive Floorplanning, power grid and signal flow planning experience</li><li>Experience in LVS, DRC, ERC, ANT, ESD, Latch-up, EMIR and Reliability</li><li>Excellent understanding of signal and clock shielding and isolation techniques</li><li>Excellent understanding of process non-idealities such as STI stress, well proximity effect and CMP effects and design strategies to mitigate these effects</li><li>Excellent written and oral communication skills are also required</li><li>Ability to work well as part of a team</li><li>Excellent problem solving skills</li><li>Strong foundation in layout design for mixed analog / digital ICs with 7nm and below CMOS process geometries experience</li><li>Experience in the layout of high performance data converters and / or high speed (GHz) circuit design would be an advantage</li><li>Extensive Floorplanning, power grid and signal flow planning experience</li><li>Experience in LVS, DRC, ERC, ANT, ESD, Latch-up, EMIR and Reliability</li><li>Excellent understanding of signal and clock shielding and isolation techniques</li><li>Excellent understanding of process non-idealities such as STI stress, well proximity effect and CMP effects and design strategies to mitigate these effects</li><li>Excellent written and oral communication skills are also required</li><li>Ability to work well as part of a team</li><li>Excellent problem solving skills</li></ul>PREFERRED EXPERIENCE: <ul><li>Must have detailed knowledge of CMOS circuit theory.</li><li>Must have ability to communicate with various teams to articulate specs and requirements as they pertain to layout</li><li>Layout design and verification experience using Cadence Virtuoso and Mentor Calibre tools</li><li>Must have at least 8 years of relevant or comparable experience doing analog layout design</li><li>Knowledge of chip level integration and ESD concepts a plus</li><li>Experience in LVS, DRC, ERC, ANT, ESD, Latch-up, EMIR and Reliability</li><li>Good understanding of signal and clock shielding and isolation techniques</li><li>Ability to work well as part of a team</li></ul>ACADEMIC CREDENTIALS: <ul style="margin: 0px; padding: 0px; font-family: verdana;"><li style="margin: 0px 0px 0px 24px; padding: 0px; font-size: 12pt; font-family: Arial, Arial_MSFontService, sans-serif;" data-leveltext="" data-font="Symbol" data-listid="12" data-list-defn-props="{"335552541":1,"335559684":-2,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" aria-setsize="-1" data-aria-posinset="2" data-aria-level="1">Bachelors or Masters degree in Electronics and Communication Engineering with 4+Yrs of exp</li></ul><p style="margin-top: 0px;margin-right: 0px;margin-bottom: 0px;margin-left: 24px;padding-top: 0px;padding-right: 0px;padding-bottom: 0px;padding-left: 0px;font-size: 12pt;font-family: Arial, Arial_MSFontService, sans-serif;"> <p style="margin-top: 0px;margin-right: 0px;margin-bottom: 0px;margin-left: 24px;padding-top: 0px;padding-right: 0px;padding-bottom: 0px;padding-left: 0px;font-size: 12pt;font-family: Arial, Arial_MSFontService, sans-serif;">#LI-SR4

Collected experience requirement

8+ years