FPGA Silicon Design Verification Engineer
Altera · Bangalore
Source and collection record
Last observed by our collector: . This is not a manual review or a confirmation from the employer.
Employer requisition: R03112
Job type and experience labels are automated discovery categories. The employer determines eligibility. Original experience wording was not retained separately; check the current employer page.
Your application evidence checklist
Mark the statements you can support after reading the employer source. This checklist stays on this page; it does not score your eligibility or submit an application.
0 of 2 checks marked. Keep unresolved requirements as questions for the employer.
Collected role description
Job Details: Job Description: From the IoT to the data center, Altera offers a broad portfolio of programmable logic solutions that allow customers to solve a wide variety of system level challenges. Be part of the talented PCIe IP design verification team We are looking for experienced IP design verification engineer Responsibility includes Create comprehensive verification plan based on FPGA IP architecture specifications and carry out all the IP verification tasks. Developing IP, subsystem or system level testbench, create tests, and necessary coverage goals based on specification to verify the implementation. Review verification and validation results against the coverage goals. Writing, analysing and achieving coverage metrics with failures debugging as well as bug filling and closure. Interfacing with 3rd party vendors for latest industry tool and methodology or VIP exposure and evaluation Understanding and enhancement of Design Verification processes in the FPGA development flow Apply advanced techniques to achieve verification and validation with the highest quality, productivity, and time to market. Provide practical, innovative solutions to complex problems. This role requires excellent communication and leadership skills and a proven ability to work with challenging schedules. Join our team of innovators to push the boundaries of what’s possible and move into the future. Qualifications: MSEE/BSEE or equivalent with 5 years of experience in IP / SoC design verification. Strong in System Verilog, UVM, Verilog Strong in coverage-based verification methodology with assertions Knowledge on PCIe is a must Familiar with Perl, Python, Java is a plus Familiarity with Intel Quartus or Xilinx Vivado is a plus. Strong skills in communication, initiative, promote innovation and teamwork Highly motivated to learn and adapt to fast changing technologies and environments Demonstrates fundamental values such as accountability, integrity and a winning mindset Job Type: Regular Shift: Shift 1 (India) Primary Location: Bengaluru, Karnataka, India Additional Locations: Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Collected experience requirement
5 years