DFX Verification Engineer
Altera · Bangalore
Source and collection record
Last observed by our collector: . This is not a manual review or a confirmation from the employer.
Employer requisition: R02797
Job type and experience labels are automated discovery categories. The employer determines eligibility. Original experience wording was not retained separately; check the current employer page.
Your application evidence checklist
Mark the statements you can support after reading the employer source. This checklist stays on this page; it does not score your eligibility or submit an application.
0 of 2 checks marked. Keep unresolved requirements as questions for the employer.
Collected role description
Job Details: Job Description: As a Sr. SoC Design Verification Engineer, you will be responsible for Design for Debug architecture verification related tasks including creating test cases and test bench using UVM methodology. Capacity could include full chip and/or system functional verification with defining verification strategies, methodology and test plan to enable effective verification. Coordinate cross functional efforts with Design, SW, Architecture team to achieve full coverage verification plan. Using system full application to verify performance and identify short falls. Responsibility Pre-silicon system verification. This include SoC, FPGA & Full Chip design verification. Create testcase and testbench with UVM methodology Fullchip/system functional verification, by defining verification strategies/methodology and test plan to enable effective verification Coordinate/interface cross functional efforts with Design, SW, Architecture team to achieve full coverage verification plan Experience on Emulation will be an add on. Qualifications: 5+ years of experience with complex ASIC designs and/or verification Familiar with System Verilog language Experience on UVM verification methodology, and formal verification method Working knowledge of scripting in Linux/ Unix environments as well as proficiency in Perl and or Python is desirable. Experience with Design for Debug (JTAG, High speed USB, PCIe based debug, Visualization of Internal Signal) architecture and design verification of same. Experience with ARM and RISC Debug Architectures is desired with focus on design verification. Any prior working experience on UltraSoC/ Tessent Embedded Analytics Debug Architecture will be a plus but not must for this position. Strong communication skills and the ability to work with a team spread across different geography sites Flexible in dynamic environment Job Type: Regular Shift: Shift 1 (India) Primary Location: Bengaluru, Karnataka, India Additional Locations: Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Collected experience requirement
5+ years