Lead Design Engineer

requirements into silicon-ready circuit architectures and collaborate with the architecture, digital, layout, verification, signal integrity, and post-silicon teams. Key Responsibilities Design and verify high-speed Ser Des blocks, including TX drivers, serializers, RX front ends, CTLEs, samplers, comparators, ADCs, DACs, PLLs, DLLs, clock dividers and distribution networks, regulators, bias circuits, and calibration loops. Translate link-level requirements into circuit specifications and optimize performance across PVT, mismatch, aging, and extracted parasitics. Develop behavioral models and support mixed-signal and top-level verification. Collaborate with layout and signal-integrity teams on physical implementation, channel/package effects, and post-layout signoff. Support tapeout, silicon bring-up, characterization, debug, and production release. Document results and participate in technical design reviews. Required Qualifications B.S. in Electrical Engineering or a related field with 3+ years of relevant experience, or an M.S. with 1+ years. Strong analog CMOS, noise, jitter, feedback, signal-integrity, and data-converter fundamentals. Hands-on transistor-level design experience with high-speed Ser Des circuits. Excellent command of Cadence Virtuoso, Spectre, Spectre RF, ADE, parasitic extraction, and mixed-signal verification flows. Strong analytical, communication, collaboration, and engineering judgment. Preferred Qualifications Experience with PAM4/NRZ Ser Des, advanced CMOS or Fin FET technologies, and standards such as Ethernet, PCIe, or CXL. MATLAB or C for architecture development; System Verilog or Verilog-A for functional modeling; and Perl or Python for automation. Experience using AI-assisted engineering tools responsibly for design exploration, verification, debugging, documentation, and workflow automation. Custom analog layout experience is a plus. Lab characterization experience is a plus, along with experience taking mixed-signal IP from architecture through tapeout and silicon validation. Success in This Role The ideal candidate combines strong circuit intuition, disciplined verification, ownership, and clear communication to deliver reliable, power-efficient Ser Des solutions. We’re doing work that matters. Help us solve what others can’t. Additional Jobs Equal Employment Opportunity Policy: Cadence is committed to equal employment opportunity throughout all levels of the organization. Read the policy(opens in a new tab) We welcome your interest in the company and want to make sure our job site is accessible to all. If you experience difficulty using this site or to request a reasonable accommodation, please contact staffing@cadence.com. Privacy Policy: Job Applicant If you are a job seeker creating a profile using our careers website, please see the privacy policy(opens in a new tab). E-Verify Cadence participates in the E-Verify program in certain U.S. locations as required by law. Download More Information on E-Verify (64K) Cadence plays a critical role in creating the technologies that modern life depends on. We are a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences. Thanks to the outstanding caliber of the Cadence team and the empowering culture that we have cultivated for over 25 years, Cadence continues to be recognized by Fortune Magazine as one of the 100 Best Companies to Work For. Our shared passion for solving the world’s toughest technical challenges, our dedication to pushing the limits of the industry, and our drive to do meaningful work differentiates the people of Cadence. Cadence is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.