Sr. Verif Engineer/Lead Verif Engineer

NXP Semiconductors · Noida

Source and collection record

Last observed by our collector: 8 October 2026 at 10:53 pm IST. This is not a manual review or a confirmation from the employer.

Employer requisition: R-10066209

Job type and experience labels are automated discovery categories. The employer determines eligibility. Original experience wording was not retained separately; check the current employer page.

How sourcing and classification work · Report a discrepancy

Your application evidence checklist

Mark the statements you can support after reading the employer source. This checklist stays on this page; it does not score your eligibility or submit an application.

Attendance and availability: I checked the employer page for work location, office attendance, start date and duration.Current requisition: I checked the current employer requisition and its application requirements.

0 of 2 checks marked. Keep unresolved requirements as questions for the employer.

Collected role description

Generic Job Description (not Job Level specific): The Digital Verification Engineer / Architect is responsible for defining Design Verification strategy, plan and implement it for a IP, sub-system or IC level. Responsible for executing Digital verification to guarantee no “functional” fault exist, according to Specifications (Test cases) defined by product architects. Author of the Verification-specific documentation for internal and external use. Can be responsible for development of models or verification environment required specifically for Digital functional verification. #LI-DNI