Leader/Manager, ASIC Design Verification Engineering || Verilog, UVM, TestBench, Technical Leadership, Hardware Emulation, SOC || Exp - 15 + years

Cisco · Bangalore

Source and collection record

Last observed by our collector: 8 October 2026 at 11:15 pm IST. This is not a manual review or a confirmation from the employer.

Employer requisition: 2025084

Job type and experience labels are automated discovery categories. The employer determines eligibility. Original experience wording was not retained separately; check the current employer page.

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Collected role description

We are recruiting an ASIC Design Verification Engineering Leader to drive high-performance ASIC design verification for Cisco's enterprise platforms. Lead teams in defining and verifying ASICs, collaborate cross-functionally, and ensure quality delivery. Ideal for experienced ASIC engineers with strong technical leadership and expertise in UVM, C++, and ASIC development.

Collected experience requirement

15 years