ASIC DFT Engineering Technical Leader | ATPG, MBIST, SSN, SCAN | 12+ years

Cisco · Bangalore

Source and collection record

Last observed by our collector: 8 October 2026 at 11:15 pm IST. This is not a manual review or a confirmation from the employer.

Employer requisition: 2020223

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Collected role description

Take on the role of ASIC DFT Engineering Technical Leader, driving the implementation of Hardware Design-for-Test (DFT) features for advanced networking chips. Lead DFT integration, collaborate with cross-functional teams, and ensure testability in chip design. Ideal for experienced engineers with deep expertise in DFT, test, and ASIC design.

Collected experience requirement

12+ years