ASIC Verification Technical Leader || Verilog, System Verilog, Testbench, UVM || Exp - 10+ years

Cisco · Bangalore

Source and collection record

Last observed by our collector: 8 October 2026 at 11:15 pm IST. This is not a manual review or a confirmation from the employer.

Employer requisition: 2023398

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Collected role description

We are recruiting a ASIC Verification Technical Leader to architect and manage the full lifecycle verification of advanced ASICs for Cisco’s core networking platforms. Lead dynamic collaboration with verification teams, ensuring robust design and integration. Ideal for experienced ASIC design and verification professionals with strong expertise in UVM/System Verilog and related tools.

Collected experience requirement

10 years