DFT Engineering Technical Lead || ATPG, SCAN, JTAG, MBIST, TestMax, Tessent || Exp - 10+ years

Cisco · Bangalore

Source and collection record

Last observed by our collector: 8 October 2026 at 11:15 pm IST. This is not a manual review or a confirmation from the employer.

Employer requisition: 2023483

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Collected role description

Join our team as a DFT Engineering Technical Lead, driving the implementation of Hardware Design-for-Test features for advanced networking hardware. Lead innovation in DFT IP development and collaborate with cross-functional teams to integrate testability. Ideal for experienced engineers with deep expertise in DFT, test, and silicon engineering.

Collected experience requirement

10 years