ASIC Engineering Design Verification Leader (SystemVerilog, Python, C and UVM |8-12 years| Pune)

Cisco · Pune

Source and collection record

Last observed by our collector: 8 October 2026 at 11:15 pm IST. This is not a manual review or a confirmation from the employer.

Employer requisition: 2013041

Job type and experience labels are automated discovery categories. The employer determines eligibility. Original experience wording was not retained separately; check the current employer page.

How sourcing and classification work · Report a discrepancy

Your application evidence checklist

Mark the statements you can support after reading the employer source. This checklist stays on this page; it does not score your eligibility or submit an application.

Attendance and availability: I checked the employer page for work location, office attendance, start date and duration.Current requisition: I checked the current employer requisition and its application requirements.

0 of 2 checks marked. Keep unresolved requirements as questions for the employer.

Collected role description

We are recruiting a ASIC Engineering Design Verification Leader to drive the design and verification of advanced optical transceivers and platforms for Cisco's data centre networking solutions. Lead verification documentation, develop testbench components, and collaborate with multidisciplinary teams. Ideal for experienced engineers with strong expertise in SystemVerilog, Python, C, and UVM.

Collected experience requirement

8-12 years