ASIC Engineering Digital Design Leader ( digital design, FSM, CPU sub-systems, complex SOCs, FPGA validation | 12-16 Years | Pune)

Cisco · Pune

Source and collection record

Last observed by our collector: 8 October 2026 at 11:15 pm IST. This is not a manual review or a confirmation from the employer.

Employer requisition: 2013153

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Collected role description

Exciting opportunity for an ASIC Engineering Digital Design Leader to provide technical leadership in the development of digital logic for silicon photonics, focusing on high-speed optical interconnects. Lead the full ASIC lifecycle and collaborate with cross-functional teams. Ideal for experienced professionals with deep expertise in digital design and ASIC/SoC design.

Collected experience requirement

12-16 Years