ASIC Engineering Digital Designer/ Leader ( digital design, FSM, CPU sub-systems, complex SOCs, FPGA validation | 8-12 Years | Pune)

Cisco · Pune

Source and collection record

Last observed by our collector: 8 October 2026 at 11:15 pm IST. This is not a manual review or a confirmation from the employer.

Employer requisition: 2013154

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Collected role description

Take on the role of Digital Design Lead for the Client Optics Group, driving technical leadership in the development of advanced digital logic for silicon photonics. Lead the full ASIC lifecycle, from RTL design to post-silicon validation, and collaborate with cross-functional teams. Ideal for experienced professionals in high-speed optical interconnects and ASIC/SoC design.

Collected experience requirement

8-12 Years